 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| mixed signal isp flash mcu family c8051f80x-83x rev. 1.0 7/10 copyright ? 2010 by silicon laboratories c8051f80x-83x capacitance to digital converter - supports buttons, sliders, wheels, and capacitive proximity sensing - fast 40 s per channel conversion time - 16-bit resolution - up to 16 input channels - auto-scan and wake-on-touch - auto-accumulate 4x, 8x, 16, 32x, and 64x samples analog peripherals - 10-bit adc ? up to 500 ksps ? up to 16 external single-ended inputs ? vref from on-chip vref, external pin or v dd ? internal or external start of conversion source ? built-in temperature sensor - comparator ? programmable hysteresis and response time ? configurable as interrupt or reset source on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - up to 512 bytes internal data ram (256 + 256) - up to 16 kb flash; in-system programmable in 512-byte sectors digital peripherals - 17 or 13 port i/o with high sink current - hardware enhanced uart, smbus? (i 2 c compati- ble), and enhanced spi? serial ports - three general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with 3 capture/compare modules and enhanced pwm functionality - real time clock mode using timer and crystal clock sources - 24.5 mhz 2% oscillator ? supports crystal-less uart operation - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - can switch between clock s ources on-the-fly; useful in power saving modes supply voltage 1.8 to 3.6 v - built-in voltage supply monitor 24-pin qsop, 20-pin qfn, 16-pin soic temperature range: ?40 to +85 c analog peripherals 16 kb isp flash 512 b ram por debug circuitry flexible interrupts 8051 cpu (25 mips) digital i/o 24.5 mhz precision internal oscillator high-speed controller core crossbar voltage comparator + ? wdt uart smbus pca timer 0 timer 1 timer 2 port 0 spi 10-bit 500 ksps adc temp sensor a m u x p1.0- p1.3 p2.0 capacitive sense p1.4- p1.7
c8051f80x-83x 2 rev. 1.0 rev. 1.0 3 c8051f80x-83x table of contents 1. system overview ........ ................ ................. ................ ................. ................ ........... 15 2. ordering information ....... ................ ................ ................. .............. .............. ........... 25 3. pin definitions........... ................ ................ ................. ................ ................. ............. 28 4. qfn-20 package specifications ..... ................ ................. .............. .............. ........... 33 5. qsop-24 package specific ations .............. ................ ................. ................ ........... 35 6. soic-16 package specific ations ................ ................ ................. ................ ........... 37 7. electrical characteristics ......... ................ ................. ................ ................. ............. 39 7.1. absolute maximum specificat ions................ .............. .............. .............. ........... 39 7.2. electrical characteri stics ................ .............. .............. .............. .............. ........... 40 8. 10-bit adc (adc0) ........ ................. ................ ................ ................. .............. ........... 46 8.1. output code formatting ....... ................. ................ ................. ................ ........... 47 8.2. 8-bit mode ....... ................. .............. .............. .............. .............. .............. ........... 47 8.3. modes of operation ... ................ ................ ................. .............. .............. ........... 47 8.3.1. starting a conversion...... ................ ................ ................. .............. ........... 47 8.3.2. tracking modes............... ................ ................ ................. .............. ........... 48 8.3.3. settling time requirement s................. .............. .............. .............. ........... 49 8.4. programmable window detector ............... ................. .............. .............. ........... 53 8.4.1. window detector example. ............... ................. .............. .............. ........... 55 8.5. adc0 analog multiplexer ..... ................. ................ ................. ................ ........... 56 9. temperature sensor ............... .............. .............. .............. .............. .............. ........... 58 9.1. calibration ..... ................ ................. .............. .............. .............. .............. ........... 58 10. voltage and ground reference options........... .............. .............. .............. ......... 60 10.1. external voltage references ................... ................. .............. .............. ........... 61 10.2. internal voltage reference options ........... .............. .............. .............. ........... 61 10.3. analog ground reference....... ................ ................. .............. .............. ........... 61 10.4. temperature sensor enable ... ................ ................. .............. .............. ........... 61 11. voltage regulator (reg0) ........ ................. ................ ................. ................ ........... 63 12. comparator0.............. ................ ................. ................ ................. ................ ........... 65 12.1. comparator multiplexer ...... ................. ................ ................. ................ ........... 69 13. capacitive sense (cs0) . ................ ................ ................. .............. .............. ........... 71 13.1. configuring port pins as capacitive sense inputs ....... ............... ........... ......... 72 13.2. capacitive sense start-of-conversion sour ces ............... ................. ............. 72 13.3. automatic scanning..... ................. .............. .............. .............. .............. ........... 72 13.4. cs0 comparator...... ................ ................ ................. .............. .............. ........... 73 13.5. cs0 conversion accumulator . ................ ................. .............. .............. ........... 74 13.6. capacitive sense multiplexe r .................. ................. .............. .............. ........... 80 14. cip-51 microcontroller.............. ................. ................ ................. ................ ........... 82 14.1. instruction set....... ................. ................ ................ ................. .............. ........... 83 14.1.1. instruction and cpu timing ............... .............. .............. .............. ........... 83 14.2. cip-51 register descriptions .. ................ ................. .............. .............. ........... 88 15. memory organization .... ................ ................ ................. .............. .............. ........... 92 15.1. program memory....... ................ ................. .............. .............. .............. ........... 93 15.1.1. movx instruction and program memory .. ................ ................. ............. 93 c8051f80x-83x 4 rev. 1.0 15.2. data memory ........... ................ ................ ................. .............. .............. ........... 93 15.2.1. internal ram ..... ................ ................. .............. .............. .............. ........... 93 15.2.1.1. general purpose regi sters ................ ................. ................ ........... 94 15.2.1.2. bit addressable locat ions ............. .............. ............... ........... ......... 94 15.2.1.3. stack ........... .............. .............. .............. .............. .............. ........... 94 16. in-system device identification ................ ................ ................. ................ ........... 95 17. special function registers...... ................. ................ ................. ................ ........... 97 18. interrupts ............ ................ ................. .............. .............. .............. .............. ......... 102 18.1. mcu interrupt sour ces and vectors........... .............. .............. .............. ......... 103 18.1.1. interrupt priorities....... ................. ................ ................. ................ ......... 103 18.1.2. interrupt latency ............. ................ ................. .............. .............. ......... 103 18.2. interrupt register descripti ons .............. ................ ................. .............. ......... 104 18.3. int0 and int1 external interrupts....... ................ ................. ................ ......... 111 19. flash memory.............. ................. ................ ................ ................. .............. ......... 113 19.1. programming the flash memo ry ............... .............. .............. .............. ......... 113 19.1.1. flash lock and key functi ons ............... .............. ............... ........... ....... 113 19.1.2. flash erase procedure ..... ................. .............. .............. .............. ......... 113 19.1.3. flash write procedure ..... ............... ................. .............. .............. ......... 114 19.2. non-volatile data storage .. ................. ................ ................. ................ ......... 114 19.3. security options ...... ................ ................ ................. .............. .............. ......... 114 19.4. flash write and erase guidel ines .............. .............. .............. .............. ......... 115 19.4.1. vdd maintenance and t he vdd monitor ...... ................. .............. ......... 116 19.4.2. pswe maintenance ............. .............. .............. .............. .............. ......... 116 19.4.3. system clock ...... ................. .............. .............. .............. .............. ......... 117 20. power management modes...... ................. ................ ................. ................ ......... 120 20.1. idle mode....... ................. .............. .............. .............. .............. .............. ......... 120 20.2. stop mode ............... ................ ................ ................. .............. .............. ......... 121 20.3. suspend mode .......... ................ ................. .............. .............. .............. ......... 121 21. reset sources ........... ................ ................. ................ ................. ................ ......... 123 21.1. power-on reset ...... ................ ................ ................. .............. .............. ......... 124 21.2. power-fail reset / vdd moni tor .................... .............. ............... ........... ....... 125 21.3. external reset ................ .............. .............. .............. .............. .............. ......... 126 21.4. missing clock detector reset . ................ ................. .............. .............. ......... 126 21.5. comparator0 reset ............ ................. ................ ................. ................ ......... 127 21.6. pca watchdog timer reset ..... ................. .............. .............. .............. ......... 127 21.7. flash error reset .... ................ ................ ................. .............. .............. ......... 127 21.8. software reset ........ ................ ................ ................. .............. .............. ......... 127 22. oscillators and clock selection ............ ................. ................ ................. ........... 129 22.1. system clock selection...... ................. ................ ................. ................ ......... 129 22.2. programmable internal high-frequency (h-f) oscillator .. ................. ........... 131 22.3. external oscillator drive circuit........ ................. ................ ................. ........... 133 22.3.1. external crystal example. ............... ................. .............. .............. ......... 135 22.3.2. external rc example...... ................ ................. .............. .............. ......... 136 22.3.3. external capacitor exam ple............... .............. .............. .............. ......... 137 23. port input/output ...... ................ ................. ................ ................. ................ ......... 138 rev. 1.0 5 c8051f80x-83x 23.1. port i/o modes of operation. ................... ................. .............. .............. ......... 139 23.1.1. port pins configured fo r analog i/o.......... ................ ................. ........... 139 23.1.2. port pins configured fo r digital i/o.......... ................ ................. ........... 139 23.1.3. interfacing port i/o to 5 v logic ................ ................ ................. ........... 140 23.2. assigning port i/ o pins to analog and digital functi ons................. .............. 140 23.2.1. assigning port i/o pins to analog f unctions ............ ................. ........... 140 23.2.2. assigning port i/o pins to digital f unctions............ ............ ........... ....... 141 23.2.3. assigning port i/o pins to external digital event capture functions ... 142 23.3. priority crossbar decoder .. ................. ................ ................. ................ ......... 143 23.4. port i/o initializatio n ................ ................ ................. .............. .............. ......... 147 23.5. port match ............ ................. ................ ................ ................. .............. ......... 150 23.6. special function regist ers for accessing an d configuring port i/o ............. 152 24. cyclic redundancy check unit (crc0).......... .............. .............. .............. ......... 159 24.1. 16-bit crc algorit hm............... ................ ................. .............. .............. ......... 160 24.2. 32-bit crc algorit hm............... ................ ................. .............. .............. ......... 161 24.3. preparing for a crc calculatio n ................ .............. .............. .............. ......... 162 24.4. performing a crc calculation . ............... ................. .............. .............. ......... 162 24.5. accessing the crc0 result .... ................ ................. .............. .............. ......... 162 24.6. crc0 bit reverse feature.... ................ ................ ................. .............. ......... 166 25. enhanced serial peripheral in terface (spi0) ......... ................ ................. ........... 167 25.1. signal descriptions.. ................ ................ ................. .............. .............. ......... 168 25.1.1. master out, slave in (m osi).............. .............. .............. .............. ......... 168 25.1.2. master in, slave out (m iso).............. .............. .............. .............. ......... 168 25.1.3. serial clock (sck ) ................. .............. .............. .............. .............. ....... 168 25.1.4. slave select (nss) ....... ................ ................ ................. .............. ......... 168 25.2. spi0 master mode op eration .............. ................ ................. ................ ......... 168 25.3. spi0 slave m ode operation .................. ................ ................. .............. ......... 170 25.4. spi0 interrupt sources ....... ................. ................ ................. ................ ......... 171 25.5. serial clock phase and polari ty .............. ................. .............. .............. ......... 171 25.6. spi special function register s .................. .............. .............. .............. ......... 173 26. smbus................. ................ ................. .............. .............. .............. .............. ......... 180 26.1. supporting document s ................. .............. .............. .............. .............. ......... 181 26.2. smbus configuration.......... ................. ................ ................. ................ ......... 181 26.3. smbus operation ...... ................ ................. .............. .............. .............. ......... 181 26.3.1. transmitter vs. receiver.. ............... ................. .............. .............. ......... 182 26.3.2. arbitration........ ................ ................ ................. .............. .............. ......... 182 26.3.3. clock low extensio n................ ................. ................ ................. ........... 182 26.3.4. scl low timeout... .............. .............. .............. .............. .............. ......... 182 26.3.5. scl high (smbus free) timeout ............... ................. ................ ......... 183 26.4. using the smbus..... ................ ................ ................. .............. .............. ......... 183 26.4.1. smbus configuration regi ster............. .............. .............. .............. ....... 183 26.4.2. smb0cn control register ................. .............. .............. .............. ......... 187 26.4.2.1. software ack generat ion .................. ................. ................ ......... 187 26.4.2.2. hardware ack generat ion ............... ................ ................. ........... 187 26.4.3. hardware slave addre ss recognition ........ ................. ................ ......... 189 c8051f80x-83x 6 rev. 1.0 26.4.4. data register .... ................ ................. .............. .............. .............. ......... 192 26.5. smbus transfer modes......... ................ ................ ................. .............. ......... 193 26.5.1. write sequence (master) .. ................. .............. .............. .............. ......... 193 26.5.2. read sequence (master) ..... .............. .............. .............. .............. ......... 194 26.5.3. write sequence (slave) ... ............... ................. .............. .............. ......... 195 26.5.4. read sequence (slave) .... ................. .............. .............. .............. ......... 196 26.6. smbus status decodi ng................... ................. ................ ................. ........... 196 27. uart0 ................. ................ ................. .............. .............. .............. .............. ......... 201 27.1. enhanced baud rate generati on............ ................. .............. .............. ......... 202 27.2. operational modes ............. ................. ................ ................. ................ ......... 203 27.2.1. 8-bit uart ........ ................ ................. .............. .............. .............. ......... 203 27.2.2. 9-bit uart ........ ................ ................. .............. .............. .............. ......... 204 27.3. multiprocessor communication s ................ .............. .............. .............. ......... 205 28. timers ................... ................. ................ ................ ................. ................ .............. 20 9 28.1. timer 0 and timer 1 ... ............... ................. .............. .............. .............. ......... 211 28.1.1. mode 0: 13-bit counter/timer ............ .............. .............. .............. ......... 211 28.1.2. mode 1: 16-bit counter/timer ............ .............. .............. .............. ......... 212 28.1.3. mode 2: 8-bit counter/timer with auto-reload.... ............... ........... ....... 212 28.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ........... ........... ....... 213 28.2. timer 2 .......... ................. .............. .............. .............. .............. .............. ......... 219 28.2.1. 16-bit timer with auto-rel oad................ .............. ............... ........... ....... 219 28.2.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 220 29. programmable counter array............ .............. .............. .............. .............. ......... 225 29.1. pca counter/timer ............ ................. ................ ................. ................ ......... 226 29.2. pca0 interrupt sources...... ................. ................ ................. ................ ......... 227 29.3. capture/compare modules ..... ................ ................. .............. .............. ......... 228 29.3.1. edge-triggered capture mode .............. .............. ............... ........... ....... 229 29.3.2. software timer (compare) mode................ ................. ................ ......... 230 29.3.3. high-speed output mode ............... ................. .............. .............. ......... 231 29.3.4. frequency output mode ............... ................ ................. .............. ......... 232 29.3.5. 8-bit through 15-bit pulse width modu lator modes ............ ........... ....... 232 29.3.5.1. 8-bit pulse width m odulator mode.......... .............. .............. ......... 233 29.3.5.2. 9-bit through 15-bit pulse width modulator mode ....... ................ 234 29.3.6. 16-bit pulse width modul ator mode........... ................. ................ ......... 235 29.4. watchdog timer mode ... .............. .............. .............. .............. .............. ......... 236 29.4.1. watchdog timer o peration .................. .............. .............. .............. ....... 236 29.4.2. watchdog timer usage ....... .............. .............. .............. .............. ......... 237 29.5. register descriptions for pc a0............. ................ ................. .............. ......... 237 30. c2 interface ............. ................ ................ ................. ................ ................. ........... 244 30.1. c2 interface registers........ ................. ................ ................. ................ ......... 244 30.2. c2ck pin sharing ... ................ ................ ................. .............. .............. ......... 247 document change list............... .............. .............. .............. .............. .............. ......... 248 contact information.......... ................. ................ ................ ................. .............. ......... 250 rev. 1.0 7 c8051f80x-83x list of tables 1. system overview 2. ordering information table 2.1. product selection guide ............... ................ ................. .............. ........... 26 3. pin definitions table 3.1. pin definitions for t he c8051f80x-83x ....... ................. ................ ........... 28 4. qfn-20 package specifications table 4.1. qfn-20 package dimensi ons ............. .............. .............. .............. ......... 33 table 4.2. qfn-20 pcb land pattern dimensions .............. ............... ........... ......... 34 5. qsop-24 packag e specifications table 5.1. qsop-24 package dimensions .......... .............. .............. .............. ......... 35 table 5.2. qsop-24 pcb land pattern dimensions ................ ................. ............. 36 6. soic-16 packag e specifications table 6.1. soic-16 package dimensi ons .............. .............. ............... ........... ......... 37 table 6.2. soic-16 pcb land patt ern dimensions .... ................. ................ ........... 38 7. electrical characteristics table 7.1. absolute maximum ratings ............... .............. .............. .............. ........... 39 table 7.2. global electrical char acteristics ............ .............. ............... ........... ......... 40 table 7.3. port i/o dc elec trical characteristics .............. .............. .............. ........... 41 table 7.4. reset electrical characteristics ......... .............. .............. .............. ........... 41 table 7.5. internal voltage regula tor electrical characteristi cs ................ ............. 41 table 7.6. flash electrical charac teristics ......... .............. .............. .............. ........... 42 table 7.7. internal high-frequency oscillator electrical char acteristics .... ............. 42 table 7.8. capacitive sense electr ical characteristics ................ ................ ........... 42 table 7.9. adc0 electrical characteristics ......... .............. .............. .............. ........... 43 table 7.10. power management el ectrical characteristics ..... ............ ........... ......... 44 table 7.11. temperature sensor electrical characteristics .... ............ ........... ......... 44 table 7.12. voltage reference electrical charac teristics ....... ............ ........... ......... 44 table 7.13. comparator electrical characteristics .... ................ ................. ............. 45 8. 10-bit adc (adc0) 9. temperature sensor 10. voltage and groun d reference options 11. voltage regulator (reg0) 12. comparator0 13. capacitive sense (cs0) table 13.1. operation with auto -scan and accumulate .......... ............ ........... ......... 74 14. cip-51 microcontroller table 14.1. cip-51 instruction set summary ............ ................ ................. ............. 84 15. memory organization 16. in-system device identification 17. special function registers table 17.1. special function r egister (sfr) memory map .... ............ ........... ......... 97 table 17.2. special function regist ers .............. .............. .............. .............. ........... 98 18. interrupts c8051f80x-83x 8 rev. 1.0 table 18.1. interrupt summary ... ................. ................ ................. ................ ......... 104 19. flash memory table 19.1. flash security summar y ................. .............. .............. .............. ......... 115 20. power management modes 21. reset sources 22. oscillators a nd clock selection 23. port input/output table 23.1. port i/o assignment for analog functions ........... ............ ........... ....... 141 table 23.2. port i/o assignment for digital functions .......... ............... ........... ....... 142 table 23.3. port i/o assignmen t for external digital event capture functions .... 142 24. cyclic redundancy check unit (crc0) table 24.1. example 16-bit crc ou tputs ............ .............. .............. .............. ....... 160 table 24.2. example 32-bit crc ou tputs ............ .............. .............. .............. ....... 161 25. enhanced serial pe ripheral interface (spi0) table 25.1. spi slave timing para meters ......... .............. .............. .............. ......... 179 26. smbus table 26.1. smbus clock source selection .............. ................ ................. ........... 184 table 26.2. minimum sda setup and hold times ...... ................. ................ ......... 185 table 26.3. sources for hardwa re changes to smb0cn ......... ................. ........... 189 table 26.4. hardware address recognition examples (ehack = 1) ........ ........... 190 table 26.5. smbus status decoding wi th hardware ack generation disabled (ehack = 0) .......... ................ ................. ................ ................. ........... 197 table 26.6. smbus status decoding wi th hardware ack generation enabled (ehack = 1) .......... ................ ................. ................ ................. ........... 199 27. uart0 table 27.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator .. ................ ................. ........... 208 table 27.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator ................ ................ ......... 208 28. timers 29. programmable counter array table 29.1. pca timebase input op tions ............ .............. .............. .............. ....... 226 table 29.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules 1,2,3,4,5,6 ................ .............. .............. .............. .............. ......... 228 table 29.3. watchdog timer timeout intervals1 ......... ................. ................ ......... 237 30. c2 interface rev. 1.0 9 c8051f80x-83x list of figures 1. system overview figure 1.1. c8051f800, c 8051f806, c8051f812, c8051f818 block diagram ..... 16 figure 1.2. c8051f801, c 8051f807, c8051f813, c8051f819 block diagram ..... 17 figure 1.3. c8051f802, c 8051f808, c8051f814, c8051f820 block diagram ..... 18 figure 1.4. c8051f803, c 8051f809, c8051f815, c8051f821 block diagram ..... 19 figure 1.5. c8051f804, c 8051f810, c8051f816, c8051f822 block diagram ..... 20 figure 1.6. c8051f805, c 8051f811, c8051f817, c8051f823 block diagram ..... 21 figure 1.7. c8051f824, c 8051f827, c8051f830, c8051f833 block diagram ..... 22 figure 1.8. c8051f825, c 8051f828, c8051f831, c8051f834 block diagram ..... 23 figure 1.9. c8051f826, c 8051f829, c8051f832, c8051f835 block diagram ..... 24 2. ordering information 3. pin definitions figure 3.1. qfn-20 pinout diagram (top view) ......... ................. ................ ........... 30 figure 3.2. qsop-24 pinout diagram (top view) .. .............. ............... ........... ......... 31 figure 3.3. soic-16 pinout diagram (top view) ... .............. ............... ........... ......... 32 4. qfn-20 package specifications figure 4.1. qfn-20 package drawin g ...................... ................ ................. ............. 33 figure 4.2. qfn-20 recommended pcb land pattern ... .............. .............. ........... 34 5. qsop-24 packag e specifications figure 5.1. qsop-24 package drawing .......... ................. .............. .............. ........... 35 figure 5.2. qsop-24 pcb land patter n ................ .............. ............... ........... ......... 36 6. soic-16 packag e specifications figure 6.1. soic-16 pack age drawing .............. .............. .............. .............. ........... 37 figure 6.2. soic-16 pcb land patter n ............... .............. .............. .............. ......... 38 7. electrical characteristics 8. 10-bit adc (adc0) figure 8.1. adc0 functional blo ck diagram ............. ................ ................. ............. 46 figure 8.2. 10-bit adc track and conversion exampl e timing ........... ............ ...... 48 figure 8.3. adc0 equival ent input circuits ........ .............. .............. .............. ........... 49 figure 8.4. adc window compare example: right-justified data ......... ................ 55 figure 8.5. adc window compare example: left-justified data ........... ................ 55 figure 8.6. adc0 multiplexer bl ock diagram ............ ................ ................. ............. 56 9. temperature sensor figure 9.1. temperature sensor transfer function ................ ............ ........... ......... 58 figure 9.2. temperature sensor error with 1-point calibrati on at 0 c .................. 59 10. voltage and groun d reference options figure 10.1. voltage reference functional block diagram ..... ............ ........... ......... 60 11. voltage regulator (reg0) 12. comparator0 figure 12.1. comparator0 function al block diagram ............. ............ ........... ......... 65 figure 12.2. comparator hysteresis plot ............... .............. ............... ........... ......... 66 figure 12.3. comparator input mu ltiplexer block diagram ...... ............ ........... ......... 69 13. capacitive sense (cs0) c8051f80x-83x 10 rev. 1.0 figure 13.1. cs0 block diagram ..... ................ ................. .............. .............. ........... 71 figure 13.2. auto-scan example ..... ................ ................. .............. .............. ........... 73 figure 13.3. cs0 multiplexer blo ck diagram ............. ................ ................. ............. 80 14. cip-51 microcontroller figure 14.1. cip-51 block diagram .. ............... ................. .............. .............. ........... 82 15. memory organization figure 15.1. c8051f80x-83x memory map ................. ................. ................ ........... 92 figure 15.2. flash program memory map ............ .............. .............. .............. ......... 93 16. in-system device identification 17. special function registers 18. interrupts 19. flash memory 20. power management modes 21. reset sources figure 21.1. reset sources ........ ................. ................ ................. ................ ......... 123 figure 21.2. power-on and vdd monitor re set timing ...... ............... ........... ....... 124 22. oscillators a nd clock selection figure 22.1. oscillator op tions ............... .............. .............. .............. .............. ....... 129 figure 22.2. external 32.768 kh z quartz crystal oscillat or connection diagram 136 23. port input/output figure 23.1. port i/o f unctional block diagram ............... .............. .............. ......... 138 figure 23.2. port i/o cell block diagram ........... .............. .............. .............. ......... 139 figure 23.3. port i/o overdrive cu rrent ................. .............. ............... ........... ....... 140 figure 23.4. priority crossbar decoder potential pin assign ments ........... ........... 144 figure 23.5. priority crossbar decoder example 1?no skip ped pins ................. 145 figure 23.6. priority crossbar decoder example 2?skipping pins ........... ........... 146 24. cyclic redundancy check unit (crc0) figure 24.1. crc0 block diagram .. ................ ................. .............. .............. ......... 159 25. enhanced serial pe ripheral interface (spi0) figure 25.1. spi blo ck diagram ........... .............. .............. .............. .............. ......... 167 figure 25.2. multiple-master mo de connection diagram .......... ................. ........... 169 figure 25.3. 3-wire single ma ster and 3-wire single sl ave mode connection diagram 169 figure 25.4. 4-wire single master mode and 4-wire slave m ode connection diagram 170 figure 25.5. master mode data/clo ck timing ............. ................. ................ ......... 172 figure 25.6. slave mode data/clock timing (ckpha = 0) .. ............... ........... ....... 172 figure 25.7. slave mode data/clock timing (ckpha = 1) .. ............... ........... ....... 173 figure 25.8. spi mast er timing (ckpha = 0) . ................. .............. .............. ......... 177 figure 25.9. spi mast er timing (ckpha = 1) . ................. .............. .............. ......... 177 figure 25.10. spi slave ti ming (ckpha = 0) ........ .............. ............... ........... ....... 178 figure 25.11. spi slave ti ming (ckpha = 1) ........ .............. ............... ........... ....... 178 26. smbus figure 26.1. smbus block diagram ................ ................. .............. .............. ......... 180 figure 26.2. typical smbus confi guration ................ ................ ................. ........... 181 rev. 1.0 11 c8051f80x-83x figure 26.3. smbus transaction ..... ................ ................. .............. .............. ......... 182 figure 26.4. typical smbus scl ge neration .............. ................. ................ ......... 184 figure 26.5. typical master writ e sequence .............. ................. ................ ......... 193 figure 26.6. typical mast er read sequence ......... .............. ............... ........... ....... 194 figure 26.7. typical slav e write sequence ........... .............. ............... ........... ....... 195 figure 26.8. typical slave read s equence ................ ................. ................ ......... 196 27. uart0 figure 27.1. uart0 block diagram ............ ................ ................. ................ ......... 201 figure 27.2. uart0 baud rate logi c ................ .............. .............. .............. ......... 202 figure 27.3. uart interconnect diagr am .............. .............. ............... ........... ....... 203 figure 27.4. 8-bit uart timing diagram ........... .............. .............. .............. ......... 203 figure 27.5. 9-bit uart timing diagram ........... .............. .............. .............. ......... 204 figure 27.6. uart multi-proce ssor mode interconnect diagram ......... ................ 205 28. timers figure 28.1. t0 mode 0 block diagr am .............. .............. .............. .............. ......... 212 figure 28.2. t0 mode 2 block diagr am .............. .............. .............. .............. ......... 213 figure 28.3. t0 mode 3 block diagr am .............. .............. .............. .............. ......... 214 figure 28.4. timer 2 16-bi t mode block diagram .. .............. ............... ........... ....... 219 figure 28.5. timer 2 8-bi t mode block diagram .. .............. .............. .............. ....... 220 29. programmable counter array figure 29.1. pca block diagram ..... ................ ................. .............. .............. ......... 225 figure 29.2. pca counter/timer bl ock diagram ......... ................. ................ ......... 226 figure 29.3. pca interrupt block diagram ................ ................ ................. ........... 227 figure 29.4. pca capture mode diagram .............. .............. ............... ........... ....... 229 figure 29.5. pca software time r mode diagram ....... ................. ................ ......... 230 figure 29.6. pca high-speed output mode diagram ...... .............. .............. ......... 231 figure 29.7. pca frequency output mode ............ .............. ............... ........... ....... 232 figure 29.8. pca 8-bit pwm mode diagram ......... .............. ............... ........... ....... 233 figure 29.9. pca 9-bit through 15-bit pwm mode diagram ..... ................. ........... 234 figure 29.10. pca 16-bit pw m mode ........... ................ ................. .............. ......... 235 figure 29.11. pca module 2 wi th watchdog timer enabled .... ................. ........... 236 30. c2 interface figure 30.1. typical c2 pin shari ng .............. ................ ................. .............. ......... 247 c8051f80x-83x 12 rev. 1.0 list of registers sfr definition 8.1. adc0cf: adc0 configuration ........ ................ ................. ............. 50 sfr definition 8.2. adc0h: adc0 data word msb ...... ................ ................. ............. 51 sfr definition 8.3. adc0l: adc0 data word lsb ............... .............. .............. ........... 51 sfr definition 8.4. adc0cn : adc0 control ........... .............. .............. .............. ........... 52 sfr definition 8.5. adc0gth: adc0 greater-than da ta high byte ...... ........... ......... 53 sfr definition 8.6. adc0gtl: adc0 greater-than data low byte ............... ............. 53 sfr definition 8.7. adc0lth: adc0 less-than data high byte ............ ........... ......... 54 sfr definition 8.8. adc0ltl: ad c0 less-than data low byte .. ........... ........... ......... 54 sfr definition 8.9. adc0mx: amux 0 channel select ................ ............ ........... ......... 57 sfr definition 10.1. ref0cn: volt age reference control .......... ............ ........... ......... 62 sfr definition 11.1. reg0cn: vo ltage regulator control .......... ............ ........... ......... 64 sfr definition 12.1. cpt0cn: com parator0 control ....... ................. ................ ........... 67 sfr definition 12.2. cpt0md: co mparator0 mode selection ....... ................. ............. 68 sfr definition 12.3. cpt0mx: co mparator0 mux selection ...... ............ ........... ......... 70 sfr definition 13.1. cs0cn: capac itive sense control .. ................. ................ ........... 75 sfr definition 13.2. cs0c f: capacitive sense configuration .............. .............. ......... 76 sfr definition 13.3. cs0dh: capac itive sense data high byte .. ........... ........... ......... 77 sfr definition 13.4. cs0d l: capacitive sense data low byte ............ .............. ......... 77 sfr definition 13.5. cs0ss: capacitive sense auto-scan st art channel ..... ............. 78 sfr definition 13.6. cs0se: c apacitive sense auto-scan end channel ...... ............. 78 sfr definition 13.7. cs0thh: capacitive sense comparator threshold high byte ... 79 sfr definition 13.8. cs0thl: capacitive sense comparator threshold low byte .... 79 sfr definition 13.9. cs0mx: c apacitive sense mux channel se lect ............ ............. 81 sfr definition 14.1. dpl: data po inter low byte ....... .............. ............... ........... ......... 88 sfr definition 14.2. dph: data pointer high byte .. .............. .............. .............. ........... 88 sfr definition 14.3. sp: stack pointe r ................. ................. .............. .............. ........... 89 sfr definition 14.4. acc: accumulator ........ ................. ................ ................. ............. 89 sfr definition 14.5. b: b r egister ............. .............. .............. .............. .............. ........... 90 sfr definition 14.6. psw: program status word .......... ................ ................. ............. 91 sfr definition 16.1. hwid: hardwa re identification byte ......... ............... ........... ......... 95 sfr definition 16.2. derivi d: derivative identification byte .............. .............. ........... 96 sfr definition 16.3. revi d: hardware revision i dentification byte ..... .............. ......... 96 sfr definition 18.1. ie: in terrupt enable .............. ................. .............. .............. ......... 105 sfr definition 18.2. ip: inte rrupt priority ............ ................ ................. .............. ......... 106 sfr definition 18.3. eie1: extended interrupt enable 1 .............. ............ ........... ....... 107 sfr definition 18.4. eie2: extended interrupt enable 2 .............. ............ ........... ....... 108 sfr definition 18.5. eip1: extended interrupt priority 1 ........... ............... ........... ....... 109 sfr definition 18.6. eip2: extended interrupt priority 2 ........... ............... ........... ....... 110 sfr definition 18.7. it01cf: int0 /int1 configuration .. ................ ................. ........... 112 sfr definition 19.1. psctl: prog ram store r/w control ................ ................ ......... 118 sfr definition 19.2. flkey: flas h lock and key ............ ................. ................ ......... 119 sfr definition 20.1. pcon: power control ............. .............. .............. .............. ......... 122 sfr definition 21.1. vdm0cn: vdd monitor control ...... ................. ................ ......... 126 rev. 1.0 13 c8051f80x-83x sfr definition 21.2. rstsrc : reset source ......... .............. .............. .............. ......... 128 sfr definition 22.1. clksel: clock select ............ .............. .............. .............. ......... 130 sfr definition 22.2. oscicl: inte rnal h-f oscillator calibrati on ................ .............. 131 sfr definition 22.3. oscicn: inte rnal h-f oscillator control .. ............... ........... ....... 132 sfr definition 22.4. oscxcn: exte rnal oscillator control ....... ............... ........... ....... 134 sfr definition 23.1. xbr0: port i/ o crossbar register 0 ......... ............... ........... ....... 148 sfr definition 23.2. xbr1: port i/ o crossbar register 1 ......... ............... ........... ....... 149 sfr definition 23.3. p0mask: port 0 mask register ..... ................ ................. ........... 151 sfr definition 23.4. p0mat: port 0 match register ... .............. ............... ........... ....... 151 sfr definition 23.5. p1mask: port 1 mask register ..... ................ ................. ........... 152 sfr definition 23.6. p1mat: port 1 match register ... .............. ............... ........... ....... 152 sfr definition 23.7. p0: port 0 .... .............. .............. .............. .............. .............. ......... 153 sfr definition 23.8. p0mdin: port 0 input mode ........... ................ ................. ........... 154 sfr definition 23.9. p0mdout: po rt 0 output mode .... ................ ................. ........... 154 sfr definition 23.10. p0skip: port 0 skip ........... ................. .............. .............. ......... 155 sfr definition 23.11. p1: port 1 .... ................ ................. ................ ................. ........... 155 sfr definition 23.12. p1mdin: port 1 input mode ......... ................ ................. ........... 156 sfr definition 23.13. p1mdout: po rt 1 output mode .... ................. ................ ......... 156 sfr definition 23.14. p1skip: port 1 skip ........... ................. .............. .............. ......... 157 sfr definition 23.15. p2: port 2 .... ................ ................. ................ ................. ........... 157 sfr definition 23.16. p2mdout: po rt 2 output mode .... ................. ................ ......... 158 sfr definition 24.1. crc0cn: crc0 control ............... ................ ................. ........... 163 sfr definition 24.2. crc0in: crc da ta input .............. ................ ................. ........... 164 sfr definition 24.3. crc0data: c rc data output ....... ................. ................ ......... 164 sfr definition 24.4. crc0auto: crc automatic control .......... ............ ........... ....... 165 sfr definition 24.5. crc0cnt: crc automatic flash sector c ount ............ ........... 165 sfr definition 24.6. crc0flip: crc bi t flip ................ ................ ................. ........... 166 sfr definition 25.1. spi0cfg: spi 0 configuration ....... ................ ................. ........... 174 sfr definition 25.2. spi0cn: spi0 control ............ .............. .............. .............. ......... 175 sfr definition 25.3. spi0ckr: spi 0 clock rate ........... ................ ................. ........... 176 sfr definition 25.4. spi0dat: spi0 data ........... ................. .............. .............. ......... 176 sfr definition 26.1. smb0cf: smbu s clock/configuration ........ ............ ........... ....... 186 sfr definition 26.2. smb0cn: smbu s control .............. ................ ................. ........... 188 sfr definition 26.3. smb0 adr: smbus slave address ......... .............. .............. ....... 191 sfr definition 26.4. smb0adm: smbus slave address mask .... ............ ........... ....... 191 sfr definition 26.5. smb0dat: smbu s data ................ ................ ................. ........... 192 sfr definition 27.1. scon0: serial port 0 control ..... .............. ............... ........... ....... 206 sfr definition 27.2. sbuf0: seri al (uart0) port data buffer . ............... ........... ....... 207 sfr definition 28.1. ckcon: clock control ............... .............. ............... ........... ....... 210 sfr definition 28.2. tcon: timer c ontrol .............. .............. .............. .............. ......... 215 sfr definition 28.3. tmod: timer m ode ................ .............. .............. .............. ......... 216 sfr definition 28.4. tl0: timer 0 low byte ......... ................. .............. .............. ......... 217 sfr definition 28.5. tl1: timer 1 low byte ......... ................. .............. .............. ......... 217 sfr definition 28.6. th0: timer 0 high byte .............. .............. ............... ........... ....... 218 sfr definition 28.7. th1: timer 1 high byte .............. .............. ............... ........... ....... 218 c8051f80x-83x 14 rev. 1.0 sfr definition 28.8. tmr2cn: timer 2 control ............. ................ ................. ........... 222 sfr definition 28.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 223 sfr definition 28.10. tmr2rlh: timer 2 reload regi ster high byte .... ........... ....... 223 sfr definition 28.11. tmr2l: timer 2 low byte .... .............. .............. .............. ......... 224 sfr definition 28.12. tmr2h timer 2 high byte ........... ................ ................. ........... 224 sfr definition 29.1. pca0cn: pca0 control ................ ................ ................. ........... 238 sfr definition 29.2. pca0md: pca0 mode ........... .............. .............. .............. ......... 239 sfr definition 29.3. pca0pwm: pca0 pwm configuration ....... ............ ........... ....... 240 sfr definition 29.4. pca0cpmn : pca0 capture/compare mode ................. ........... 241 sfr definition 29.5. pca0l: pca0 counter/timer low byte ...... ............ ........... ....... 242 sfr definition 29.6. pca0h: pca0 counter/timer high byte ..... ............ ........... ....... 242 sfr definition 29.7. pca0cpln: pca0 capture module low byte ................ ........... 243 sfr definition 29.8. pca0cphn: pca0 capture module high byte .............. ........... 243 c2 register definition 30.1. c2ad d: c2 address ....... .............. ............... ........... ....... 244 c2 register definition 30.3. revid: c2 revision id ................. ............... ........... ....... 245 c2 register definition 30.2. deviceid: c2 device id .............. ............... ........... ....... 245 c2 register definition 30.4. fpctl: c2 flash programming control ... .............. ....... 246 c2 register definition 30.5. fpdat: c2 flas h programming data ....... .............. ....... 246 rev. 1.0 15 c8051f80x-83x 1. system overview c8051f80x-83x devices are fully integrated, mixed-si gnal, system-on-a-chip capacitive sensing mcus. highlighted features are listed below. refer to table 2 .1 for specific product feature selection and part ordering numbers. ?? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ?? in-system, full-speed, non-intrus ive debug interface (on-chip) ?? capacitive sense interface with 16 input channels ?? 10-bit 500 ksps single-ended adc with 16-channel anal og multiplexer and integrated temperature sensor ?? precision calibrated 24.5 mhz internal oscillator ?? 16 kb of on-chip flash memory ?? 512 bytes of on-chip ram ?? smbus/i 2 c, enhanced uart, and enhanced spi serial interfaces implemented in hardware ?? three general-purpose 16-bit timers ?? programmable counter/timer array (pca) with three capture/compare modules ?? on-chip internal voltage reference ?? on-chip watchdog timer ?? on-chip power-on reset and supply monitor ?? on-chip voltage comparator ?? 17 general purpose i/o with on-chip power-on reset, v dd monitor, watchdog timer, and cl ock oscillator, the c8051f80x-83x devices are truly stand-alone, system-on-a-chip so lutions. the flash memory can be reprogrammed even in-circuit, providing non-vo latile data storage, and also allowing field upgrades of th e 8051 firmware. user software has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the c8051f80x-83x processors incl ude silicon laboratories? 2-wire c2 debug and pr ogramming inter- face, which allows non-intrusive (uses no on-chip resour ces), full speed, in-circuit debugging using the pro- duction mcu installed in the final ap plication. this debug logic supports inspection of memory, viewing and modification of special function registers, setting br eakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in- system debugging without occupying package pins. each device is specified for 1.8?3.6 v operation over the industrial temperature range (?45 to +85 c). an internal ldo regulator is used to supply the proc essor core voltage at 1.8 v. the port i/o and rst pins are tolerant of input signals up to 5 v. see table 2.1 for ordering information. block diagrams of the devices in the c8051f80x-83x family are shown in figure 1.1 through figure 1.9. c8051f80x-83x 16 rev. 1.0 figure 1.1. c8051f800, c8051f806, c8051f812, c8051f818 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f800/6: 16 kb ?f812/8: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f800, ?f812 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0/c2d p1.6 p1.7 timer 2 / rtc a m u x analog peripherals vreg output vreg output capacitive sense 16 channels 16 channels rev. 1.0 17 c8051f80x-83x figure 1.2. c8051f801, c8051f807, c8051f813, c8051f819 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f801/7: 16 kb ?f813/9: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus capacitive sense (?f801, ?f813 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0/c2d p1.6 p1.7 timer 2 / rtc a m u x analog peripherals vreg output vreg output 8 channels 16 channels c8051f80x-83x 18 rev. 1.0 figure 1.3. c8051f802, c8051f808, c8051f814, c8051f820 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f802/8: 16 kb ?f814, ?f820: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f802, ?f814 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0/c2d p1.6 p1.7 timer 2 / rtc a m u x analog peripherals vreg output vreg output 16 channels rev. 1.0 19 c8051f80x-83x figure 1.4. c8051f803, c8051f809, c8051f815, c8051f821 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f803/9: 16 kb ?f815, ?f821: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f803, ?f815 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output capacitive sense 12 channels 12 channels c8051f80x-83x 20 rev. 1.0 figure 1.5. c8051f804, c8051f810, c8051f816, c8051f822 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f804, ?f810: 16 kb ?f816, ?f822: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f804, ?f816 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output capacitive sense 8 channels 12 channels rev. 1.0 21 c8051f80x-83x figure 1.6. c8051f805, c8051f811, c8051f817, c8051f823 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f805, ?f811: 16 kb ?f817, ?f823: 8 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d 256 byte xram xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f805, ?f817 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output 12 channels c8051f80x-83x 22 rev. 1.0 figure 1.7. c8051f824, c8051f827, c8051f830, c8051f833 block diagram system clock configuration debug / programming hardware cip-51 8051 controller core flash memory ?f824, ?f827: 8 kb ?f830, ?f833: 4 kb 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f824, ?f830 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output capacitive sense 12 channels 12 channels rev. 1.0 23 c8051f80x-83x figure 1.8. c8051f825, c8051f828, c8051f831, c8051f834 block diagram system clock configuration debug / programming hardware external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f825, ?f831 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output capacitive sense 8 channels 12 channels cip-51 8051 controller core flash memory ?f825, ?f828: 8 kb ?f831, ?f834: 4 kb 256 byte ram c8051f80x-83x 24 rev. 1.0 figure 1.9. c8051f826, c8051f829, c8051f832, c8051f835 block diagram system clock configuration debug / programming hardware external clock circuit precision internal oscillator xtal2 power on reset reset p2.0/c2d xtal1 regulator core power vdd gnd peripheral power 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus (?f826, ?f832 only) rst/c2ck sysclk digital peripherals uart timers 0, 1 pca/ wdt smbus priority crossbar decoder crossbar control port i/o configuration spi port 0 drivers p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers p1.0 p1.1 p1.2 p1.3 port 2 drivers p2.0/c2d timer 2 / rtc a m u x analog peripherals vreg output vreg output 12 channels cip-51 8051 controller core flash memory ?f826, ?f829: 8 kb ?f832, ?f835: 4 kb 256 byte ram rev. 1.0 25 c8051f80x-83x 2. ordering information all c8051f80x-83x devices have the following features: ? 25 mips (peak) ? calibrated internal oscillator ? smbus/i2c ? enhanced spi ? uart ? programmable counter array (3 channels) ? 3 timers (16-bit) ? 1 comparator ? pb-free (rohs compliant) package in addition to the features listed ab ove, each device in the c8051f80x-83x family has a set of features that vary across the product line. see table 2.1 for a complete list of the unique feature sets for each device in the family. c8051f80x-83x 26 rev. 1.0 table 2.1. product selection guide part number digital port i/os capacitive sense channels flash memory (kb) ram (bytes) 10-bit 500 ksps adc adc channels temperature sensor package (rohs) c8051f800-gu 17 16 16 512 ? 16 ? qsop-24 c8051f801-gu 17 8 16 512 ? 16 ? qsop-24 c8051f802-gu 17 ? 16 512 ? 16 ? qsop-24 c8051f800-gm 17 16 16 512 ? 16 ? qfn-20 c8051f801-gm 17 8 16 512 ? 16 ? qfn-20 c8051f802-gm 17 ? 16 512 ? 16 ? qfn-20 c8051f803-gs 13 12 16 512 ? 12 ? soic-16 c8051f804-gs 13 8 16 512 ? 12 ? soic-16 c8051f805-gs 13 ? 16 512 ? 12 ? soic-16 c8051f806-gu 17 16 16 512 ? ? ? qsop-24 c8051f807-gu 17 8 16 512 ? ? ? qsop-24 c8051f808-gu 17 ? 16 512 ? ? ? qsop-24 c8051f806-gm 17 16 16 512 ? ? ? qfn-20 c8051f807-gm 17 8 16 512 ? ? ? qfn-20 c8051f808-gm 17 ? 16 512 ? ? ? qfn-20 c8051f809-gs 13 12 16 512 ? ? ? soic-16 c8051f810-gs 13 8 16 512 ? ? ? soic-16 c8051f811-gs 13 ? 16 512 ? ? ? soic-16 c8051f812-gu 17 16 8 512 ? 16 ? qsop-24 c8051f813-gu 17 8 8 512 ? 16 ? qsop-24 c8051f814-gu 17 ? 8 512 ? 16 ? qsop-24 c8051f812-gm 17 16 8 512 ? 16 ? qfn-20 c8051f813-gm 17 8 8 512 ? 16 ? qfn-20 c8051f814-gm 17 ? 8 512 ? 16 ? qfn-20 c8051f815-gs 13 12 8 512 ? 12 ? soic-16 c8051f816-gs 13 8 8 512 ? 12 ? soic-16 c8051f817-gs 13 ? 8 512 ? 12 ? soic-16 c8051f818-gu 17 16 8 512 ? ? ? qsop-24 c8051f819-gu 17 8 8 512 ? ? ? qsop-24 c8051f820-gu 17 ? 8 512 ? ? ? qsop-24 c8051f818-gm 17 16 8 512 ? ? ? qfn-20 c8051f819-gm 17 8 8 512 ? ? ? qfn-20 c8051f820-gm 17 ? 8 512 ? ? ? qfn-20 rev. 1.0 27 c8051f80x-83x c8051f821-gs 13 12 8 512 ? ? ? soic-16 c8051f822-gs 13 8 8 512 ? ? ? soic-16 c8051f823-gs 13 ? 8 512 ? ? ? soic-16 c8051f824-gs 13 12 8 256 ? 12 ? soic-16 c8051f825-gs 13 8 8 256 ? 12 ? soic-16 c8051f826-gs 13 ? 8 256 ? 12 ? soic-16 c8051f827-gs 13 12 8 256 ? ? ? soic-16 c8051f828-gs 13 8 8 256 ? ? ? soic-16 c8051f829-gs 13 ? 8 256 ? ? ? soic-16 c8051f830-gs 13 12 4 256 ? 12 ? soic-16 C8051F831-GS 13 8 4 256 ? 12 ? soic-16 c8051f832-gs 13 ? 4 256 ? 12 ? soic-16 c8051f833-gs 13 12 4 256 ? ? ? soic-16 c8051f834-gs 13 8 4 256 ? ? ? soic-16 c8051f835-gs 13 ? 4 256 ? ? ? soic-16 lead finish material on all devices is 100% matte tin (sn). table 2.1. product selection guide (continued) part number digital port i/os capacitive sense channels flash memory (kb) ram (bytes) 10-bit 500 ksps adc adc channels temperature sensor package (rohs) c8051f80x-83x 28 rev. 1.0 3. pin definitions table 3.1. pin definitions for the c8051f80x-83x name pin qsop-24 pin qfn-20 pin soic-16 type description gnd 5 2 4 ground. this ground connection is required. the center pad may optionally be connected to ground as well on the qfn-20 packages. v dd 6 3 5 power supply voltage. rst / 7 4 6 d i/o device reset. open-drain output of internal por or v dd monitor. an external source can ini- tiate a system reset by driving this pin low for at least 10 s. c2ck d i/o clock signal for the c2 debug interface. p2.0/ 8 5 7 d i/o bi-directional data signal for the c2 debug inter- face. shared with p2.0 on 20-pin packaging and p2.4 on 24-pin packaging. c2d d i/o bi-directional data signal for the c2 debug inter- face. shared with p2.0 on 20-pin packaging and p2.4 on 24-pin packaging. p0.0/ 4 1 3 d i/o or a in port 0.0. vref a in external vref input. p0.1 3 20 2 d i/o or a in port 0.1. p0.2/ 2 19 1 d i/o or a in port 0.2. xtal1 a in external clock input. this pin is the external oscillator return for a crystal or resonator. p0.3/ 23 18 16 d i/o or a in port 0.3. xtal2 a i/o or d in external clock output. for an external crystal or resonator, this pin is the excitation driver. this pin is the external cloc k input for cmos, capaci- tor, or rc oscilla tor configurations. p0.4 22 17 15 d i/o or a in port 0.4. rev. 1.0 29 c8051f80x-83x p0.5 21 16 14 d i/o or a in port 0.5. p0.6/ 20 15 13 d i/o or a in port 0.6. cnvstr d in adc0 external conv ert start or ida0 update source input. p0.7 19 14 12 d i/o or a in port 0.7. p1.0 18 13 11 d i/o or a in port 1.0. p1.1 17 12 10 d i/o or a in port 1.1. p1.2 16 11 9 d i/o or a in port 1.2. p1.3 15 10 8 d i/o or a in port 1.3. p1.4 14 9 d i/o or a in port 1.4. p1.5 11 8 d i/o or a in port 1.5. p1.6 10 7 d i/o or a in port 1.6. p1.7 9 6 d i/o or a in port 1.7. nc 1, 12, 13, 24 no connection. table 3.1. pin definitions for the c8051f80x-83x (continued) name pin qsop-24 pin qfn-20 pin soic-16 type description c8051f80x-83x 30 rev. 1.0 figure 3.1. qfn-20 pinout diagram (top view) 3 4 5 1 2 8 9 10 6 7 13 12 11 15 14 18 19 20 16 17 p0.0 gnd vdd p2.0/c2d p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 c8051f80x-gm c8051f81x-gm c8051f82x-gm top view gnd rst/c2ck rev. 1.0 31 c8051f80x-83x figure 3.2. qsop-24 pinout diagram (top view) 2 1 4 3 5 6 7 top view c8051f80x-gu c8051f81x-gu c8051f82x-gu p0.2 p0.1 p0.0 gnd nc p2.0/c2d 8 p1.7 rst / c2ck 9 10 11 vdd p1.5 12 nc 23 24 21 22 20 19 18 17 16 15 14 13 p0.3 p0.4 p0.5 p0.6 nc p1.0 p1.1 p1.2 p1.4 nc p1.6 p1.3 p0.7 c8051f80x-83x 32 rev. 1.0 figure 3.3. soic-16 pinout diagram (top view) 2 1 4 3 5 6 7 15 16 13 14 12 11 10 top view c8051f80x-gs c8051f81x-gs c8051f82x-gs c8051f83x-gs p0.1 p0.0 gnd vdd p0.2 p2.0/c2d p0.7 p0.4 p0.3 p0.5 p0.6 p1.0 p1.1 8 p1.3 9 p1.2 rst / c2ck rev. 1.0 33 c8051f80x-83x 4. qfn-20 package specifications figure 4.1. qfn-20 package drawing table 4.1. qfn-20 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 l 0.45 0.55 0.65 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc. bbb ? ? 0.10 d2 2.00 2.15 2.25 ddd ? ? 0.05 e 0.50 bsc. eee ? ? 0.08 e 4.00 bsc. z ? 0.43 ? e2 2.00 2.15 2.25 y ? 0.18 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. ? c8051f80x-83x 34 rev. 1.0 figure 4.2. qfn-20 recommended pcb land pattern table 4.2. qfn-20 pcb land pattern dimensions dimension min max dimension min max c1 3.70 x2 2.15 2.25 c2 3.70 y1 0.90 1.00 e 0.50 y2 2.15 2.25 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 0.95 mm openings on a 1.1 mm pitch should be used for the center pad to assure the proper paste volume. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components. rev. 1.0 35 c8051f80x-83x 5. qsop-24 package specifications figure 5.1. qsop-24 package drawing table 5.1. qsop-24 package dimensions dimension min nom max dimension min nom max a ? ? 1.75 l 0.40 ? 1.27 a1 0.10 ? 0.25 l2 0.25 bsc b 0.20 ? 0.30 ? 0o ? 8o c0.10 ? 0.25 aaa 0.20 d 8.65 bsc bbb 0.18 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.10 e 0.635 bsc notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-137, variation ae. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051f80x-83x 36 rev. 1.0 figure 5.2. qsop-24 pcb land pattern table 5.2. qsop-24 pcb land pattern dimensions dimension min max c5.205.30 e 0.635 bsc x0.300.40 y1.501.60 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pa d size should be 1:1 for all perimeter pads. card assembly 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components. ? rev. 1.0 37 c8051f80x-83x 6. soic-16 packa ge specifications figure 6.1. soic-16 package drawing table 6.1. soic-16 package dimensions dimension min nom max dimension min nom max a ? 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 ? h 0.25 0.50 b 0.31 0.51 ? 0o 8o c0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051f80x-83x 38 rev. 1.0 figure 6.2. soic-16 pcb land pattern table 6.2. soic-16 pcb land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 3. all feature sizes shown are at maximum material co ndition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. rev. 1.0 39 c8051f80x-83x 7. electrical characteristics 7.1. absolute m aximum specifications table 7.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst or any port i/o pin with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd and gnd ??500ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. c8051f80x-83x 40 rev. 1.0 7.2. electrical characteristics table 7.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units supply voltage 1.8 3.0 3.6 v digital supply current with cpu active (normal mode 1 ) v dd = 1.8 v, clock = 25 mhz v dd = 1.8 v, clock = 1 mhz v dd = 1.8 v, clock = 32 khz v dd = 3.0 v, clock = 25 mhz v dd = 3.0 v, clock = 1 mhz v dd = 3.0 v, clock = 32 khz ? ? ? ? ? ? 4.6 1.2 135 5.5 1.3 150 6.0 ? ? 6.5 ? ? ma ma a ma ma a digital supply current with cpu inactive (idle mode 1 ) v dd = 1.8 v, clock = 25 mhz v dd = 1.8 v, clock = 1 mhz v dd = 1.8 v, clock = 32 khz v dd = 3.0 v, clock = 25 mhz v dd = 3.0 v, clock = 1 mhz v dd = 3.0 v, clock = 32 khz ? ? ? ? ? ? 2 190 100 2.3 335 115 2.6 ? ? 2.8 ? ? ma a a ma a a digital supply current (shutdown) oscillator not running (stop mode), internal regulator off, 25 c ?0.5 2 a oscillator not running (stop or suspend mode), internal regulator on, 25 c ?105140a digital supply ram data retention voltage ?1.3? v specified operating tempera- ture range ?40 ? +85 c sysclk (system clock frequency) see note 2 0 ? 25 mhz tsysl (sysclk low time) 18 ? ? ns tsysh (sysclk high time) 18 ? ? ns notes: 1. includes bias current for internal voltage regulator. 2. sysclk must be at least 32 khz to enable debugging. rev. 1.0 41 c8051f80x-83x table 7.3. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ?0.7 v dd -0.1 ? ? ? v dd -0.8 ? ? ? v v v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v v v input high voltage 0.75 x v dd ??v input low voltage ? ? 0.6 v input leakage current weak pullup off weak pullup on, v in = 0 v ?1 ? ? 15 1 50 a a table 7.4. reset electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 1.8v to 3.6v ??0.6v rst input high voltage 0.75 x v dd ?? v rst input low voltage ? ? 0.3 x v dd v dd rst input pullup current rst = 0.0 v ? 25 50 a v dd por ramp time ? ? 1 ms v dd monitor threshold (v rst ) 1.7 1.75 1.8 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 500 1000 s reset time delay delay between release of any reset source and code execution at location 0x0000 ??30s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time v dd = v rst ? 0.1 v ? 50 ? s v dd monitor supply current ? 20 30 a table 7.5. internal voltage regulator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1.8 ? 3.6 v bias current ? 50 65 a c8051f80x-83x 42 rev. 1.0 table 7.6. flash electrical characteristics parameter conditions min typ max units flash size (note 1) c8051f80x and c8051f810/1 c8051f812/3/4/5/6/7/8/9 and c8051f82x c8051f830/1/2/3/4/5 16384 8192 4096 bytes bytes bytes endurance (erase/write) 10000 ? ? cycles erase cycle time 25 mhz clock 15 20 26 ms write cycle time 25 mhz clock 15 20 26 s clock speed during flash write/erase operations 1??mhz note: includes security lock byte. table 7.7. internal high-frequency oscillator electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied. use factory-calibrated settings. parameter conditions min typ max units oscillator frequency ifcn = 11b 24 24.5 25 mhz oscillator supply current 25 c, v dd = 3.0 v, oscicn.7 = 1, ocsicn.5 = 0 ? 350 650 a table 7.8. capacitive sense electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified. parameter conditions min typ max units conversion time single conversion 26 38 50 s capacitance per code ? 1 ? ff external capacitive load ? ? 45 pf quantization noise 1 rms peak-to-peak ? ? 3 20 ? ? ff ff supply current cs module bias current, 25 c cs module alone, maximum code output, 25 c wake-on-cs threshold 2 , 25 c ? ? ? 40 75 150 60 105 165 a a a notes: 1. rms noise is equivalent to one standard deviation. peak-to-peak noise encompasses 3.3 standard deviations. 2. includes only current from regulator, cs module, and mcu in suspend mode. rev. 1.0 43 c8051f80x-83x table 7.9. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error ?2 0 2 lsb full scale error ?2 0 2 lsb offset temperature coefficient ? 45 ? ppm/c dynamic performance (10 khz sine-wave single- ended input, 1 db below full scale, 200 ksps) signal-to-noise plus distortion 54 60 ? db total harmonic distortion up to the 5th harmonic ? 75 ? db spurious-free dynamic range ? ?90 ? db conversion rate sar conversion clock ? ? 8.33 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks clocks track/hold acquisition time v dd >= 2.0 v v dd < 2.0 v 300 2.0 ? ? ? ? ns s throughput rate ? ? 500 ksps analog inputs adc input voltage range 0 ? vref v sampling capacitance 1x gain 0.5x gain ? ? 5 3 ? ? pf pf input multiplexer impedance ? 5 ? k ? power specifications power supply current operating mode, 500 ksps ? 630 1000 a power supply rejection ? ?70 ? db c8051f80x-83x 44 rev. 1.0 table 7.10. power management electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied. use factory-calibrated settings. parameter conditions min typ max units idle mode wake-u p time 2 ? 3 sysclks suspend mode wake-up time ? 500 ? ns table 7.11. temperature sensor electrical characteristics v dd = 3.0 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 1 ? c slope ? 2.43 ? mv/c slope error* ? 45 ? v/c offset temp = 0 c ? 873 ? mv offset error* temp = 0 c ? 14.5 ? mv *note: represents one standard deviation from the mean. table 7.12. voltage reference electrical characteristics v dd = 1.8 to 3.6 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal high speed reference (refsl[1:0] = 11) output voltage 25 c ambient 1.55 1.65 1.75 v turn-on time ? ? 1.7 s supply current ? 180 ? a external reference (ref0e = 0) input voltage range 0 ? v dd input current sample rate = 500 ksps; vref = 3.0 v ? 7 ? a rev. 1.0 45 c8051f80x-83x table 7.13. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 220 ? ns cp0+ ? cp0? = ?100 mv ? 225 ? ns response time: mode 1, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 340 ? ns cp0+ ? cp0? = ?100 mv ? 380 ? ns response time: mode 2, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 510 ? ns cp0+ ? cp0? = ?100 mv ? 945 ? ns response time: mode 3, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 1500 ? ns cp0+ ? cp0? = ?100 mv ? 5000 ? ns common-mode rejection ratio ? 1 4 mv/v positive hysteresis 1 mode 2, cp0hyp1?0 = 00b ? 0 1 mv positive hysteresis 2 mode 2, cp0hyp1?0 = 01b 2 5 10 mv positive hysteresis 3 mode 2, cp0hyp1?0 = 10b 7 10 20 mv positive hysteresis 4 mode 2, cp0hyp1?0 = 11b 10 20 30 mv negative hysteresis 1 mode 2, cp0hyn1?0 = 00b ? 0 1 mv negative hysteresis 2 mode 2, cp0hyn1?0 = 01b 2 5 10 mv negative hysteresis 3 mode 2, cp0hyn1?0 = 10b 7 10 20 mv negative hysteresis 4 mode 2, cp0hyn1?0 = 11b 10 20 30 mv inverting or non- inverting input voltage range ?0.25 ? v dd + 0.25 v input offset voltage ?7.5 ? 7.5 mv power specifications power supply rejection ? 0.1 ? mv/v powerup time ? 10 ? s supply current at dc mode 0 ? 20 ? a mode 1 ? 8 ? a mode 2 ? 3 ? a mode 3 ? 0.5 ? a note: vcm is the common-mode voltage on cp0+ and cp0?. c8051f80x-83x 46 rev. 1.0 8. 10-bit adc (adc0) adc0 on the c8051f800/1/2/3/4/5, c8051f812/3/4/ 5/6/7, c8051f824/5/6, and c8051f830/1/2 is a 500 ksps, 10-bit successive-approximation-register (sar) adc with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector. the adc is fully configurable under software control via special function registers. the adc may be configured to measure various dif- ferent signals using the analog multiplexer described in section ?8.5. adc0 analog multiplexer? on page 56. the voltage reference for the adc is selected as described in section ?9. temperature sensor? on page 58. the adc0 subsystem is enabled only when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1. the a dc0 subsystem is in low power shut down when this bit is logic 0. figure 8.1. adc0 functional block diagram adc0cf amp0gn0 ad08be ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic adc0ltl adc0gth adc0gtl adc0l ain from amux0 x1 or x0.5 amp0gn0 rev. 1.0 47 c8051f80x-83x 8.1. output code formatting the adc measures the input voltage with reference to gnd. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the ad0ljst bit. conversion codes are represented as 10-bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. example codes are shown below for both right-justified and left -justified data. unused bits in the adc0h and adc0l registers are set to 0. 8.2. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8-bit mode. in 8-bit mode, only the 8 msbs of data are converted, and the adc0h register holds the results. the ad0ljst bit is ignored for 8- bit mode. 8-bit conversions take two fewer sar clock cycles than 10-bit conversions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower sar clock. 8.3. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 8.3.1. starting a conversion a conversion can be initiated in one of six ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the fol- lowing: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., ti med continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). when polling for adc conversion comp letions, the adc0 interrup t flag (ad0int) should be used. converted data is available in the adc0 data registers, adc0h:adc0l, wh en bit ad0int is logic 1. when timer 2 overflows are used as the conversion sour ce, low byte overflows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2 is in 16-bit mode. see section ?28. timers? on page 209 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port i/o pin. when the cnvstr input is used as t he adc0 conversion source, the associated pin should be skipped by the digi- tal crossbar. see section ?23. port input/output? on page 138 for details on port i/o configuration. input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 c8051f80x-83x 48 rev. 1.0 8.3.2. tracking modes the ad0tm bit in register adc0cn enables "delayed conversions" , and will delay the actual conversion start by three sar clock cycles, during which time t he adc will continue to track th e input. if ad0tm is left at logic 0, a conversion will begin im mediately, without the extra tracking time. for internal start-of-conver- sion sources, the adc will track anyt ime it is not pe rforming a conver sion. when the cnvstr signal is used to initiate conversions, adc0 will track either when ad0tm is logic 1, or when ad0tm is logic 0 and cnvstr is held low. see figure 8.2 for track and convert timing details. delayed conversion mode is use- ful when amux settings are frequently changed, due to the settling time requirements described in section ?8.3.3. settling time requirements? on page 49. figure 8.2. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1 overflow (ad0cm[2:0]=000, 001, 010, 011) ad0tm=1 track convert track ad0tm=0 track or convert convert track sar clocks sar clocks b. adc timing for internal trigger source cnvstr (ad0cm[2:0]=1xx) ad0tm=1 a. adc timing for ex ternal trigger source track convert n/c ad0tm=0 track convert track *conversion ends at rising edge of 12 th clock in 8-bit mode *conversion ends at rising edge of 15 th clock in 8-bit mode *conversion ends at rising edge of 12 th clock in 8-bit mode 123456789 10 11 12* 13 14 123456789 10 11 12 13 14 15* 16 17 n/c sar clocks *conversion ends at rising edge of 15 th clock in 8-bit mode sar clocks 123456789 10 11 12 13 14 15* 16 17 123456789 10 11 12* 13 14 rev. 1.0 49 c8051f80x-83x 8.3.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per- formed. this tracking time is determined by any se ries impedance, including the amux0 resistance, the the adc0 sampling capacitance, and the accuracy required for the conversion. in delayed tracking mode, three sar clocks are used for tracking at the start of every conversion. for many applications, these three sar clocks will meet the minimum tracking time requirements. figure 8.3 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 8. 1. see table 7.9 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 8.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). figure 8.3. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? ln = r mux c sample rc input = r mux * c sample mux select input pin note: see electrical specification tables for r mux and c sample parameters. c8051f80x-83x 50 rev. 1.0 sfr address = 0xbc sfr definition 8.1. adc0cf : adc0 configuration bit76543210 name ad0sc[4:0] ad0ljst ad08be amp0gn0 type r/w r/w r/w r/w reset 11111001 bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table. 2ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. note: the ad0ljst bit is only valid for 10-bit mode (ad08be = 0). 1ad08be 8-bit mode enable. 0: adc operates in 10-bit mode (normal). 1: adc operates in 8-bit mode. note: when ad08be is set to 1, the ad0ljst bit is ignored. 0amp0gn0 adc gain control bit. 0: gain = 0.5 1: gain = 1 ad0sc sysclk clk sar ------------ ---------- -1 ? = rev. 1.0 51 c8051f80x-83x sfr address = 0xbe sfr address = 0xbd sfr definition 8.2. adc0h: adc0 data word msb bit76543210 name adc0h[7:0] type r/w reset 00000000 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7 ? 2 will read 000000b. bits 1 ? 0 are the upper 2 bits of the 10- bit adc0 data word. for ad0ljst = 1: bits 7 ? 0 are the most-significant bits of the 10-bit adc0 data word. note: in 8-bit mode ad0ljst is ignored, and adc0h holds the 8-bit data word. sfr definition 8.3. adc0l: adc0 data word lsb bit76543210 name adc0l[7:0] type r/w reset 00000000 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7 ? 0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7 ? 6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will always read 0. note: in 8-bit mode ad0ljst is ignored, and adc0l will read back 00000000b. c8051f80x-83x 52 rev. 1.0 sfr address = 0xe8; bit-addressable sfr definition 8.4. adc0cn: adc0 control bit76543210 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con- version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: delayed track mode: when adc0 is enabled, input is tracked when a conversion is not in progress. a start-of-conversion sign al initiates three sar clocks of additional tracking, and then begins the conversion. 5ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conver- sion if ad0cm[2 : 0] = 000b 3 ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2:0] adc0 start of conversion mode select. 000: adc0 start-of-conversion s ource is write of 1 to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101?111: reserved. rev. 1.0 53 c8051f80x-83x 8.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr address = 0xc4 sfr address = 0xc3 sfr definition 8.5. adc0gth: adc 0 greater-than data high byte bit76543210 name adc0gth[7:0] type r/w reset 11111111 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 8.6. adc0gtl: adc 0 greater-than data low byte bit76543210 name adc0gtl[7:0] type r/w reset 11111111 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits. c8051f80x-83x 54 rev. 1.0 sfr address = 0xc6 sfr address = 0xc5 sfr definition 8.7. adc0lth: adc0 less-than data high byte bit76543210 name adc0lth[7:0] type r/w reset 00000000 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 8.8. adc0ltl: a dc0 less-than data low byte bit76543210 name adc0ltl[7:0] type r/w reset 00000000 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits. rev. 1.0 55 c8051f80x-83x 8.4.1. window detector example figure 8.4 shows two example window comparisons for right-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if th e adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right exam ple, and ad0wint interr upt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 8.5 shows an example using left-justi- fied data with the same comparison values. figure 8.4. adc window compare example: right-justified data figure 8.5. adc window compare example: left-justified data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl c8051f80x-83x 56 rev. 1.0 8.5. adc0 analog multiplexer adc0 on the c8051f800/1/2/3/4/5, c8051f812/3/4/5/6/7, c8051f824/5/6, and c8051f830/1/2 uses an analog input multiplexer to select the positive input to the adc. any of the following may be selected as the positive input: port 0 or port 1 i/o pins, the on-ch ip temperature sensor, or the positive power supply (v dd ). the adc0 input channel is selected in the adc0 mx register described in sfr definition 8.9. figure 8.6. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by th e digital crossbar. to configure a port pin for analog input, set the corresponding bit in register pnmdin to 0. to force the crossbar to skip a port pin, set the corresponding bit in register pnskip to 1. see section ?23. port input/output? on page 138 for more port i/o configuration details. adc0 temp sensor amux vreg output adc0mx amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 p0.0 p1.7 vdd gnd note: p1.4-p1.7 are not available on the 16-pin packages. rev. 1.0 57 c8051f80x-83x sfr address = 0xbb sfr definition 8.9. adc0mx: amux0 channel select bit76543210 name amx0p[3:0] type rrr r/w reset 00011111 bit name function 7:5 unused read = 000b; write = don?t care. 4:0 amx0p[4:0] amux0 positive input selection. 20-pin and 24-pin devices 16-pin devices 00000: p0.0 p0.0 00001: p0.1 p0.1 00010: p0.2 p0.2 00011: p0.3 p0.3 00100: p0.4 p0.4 00101: p0.5 p0.5 00110: p0.6 p0.6 00111: p0.7 p0.7 01000 p1.0 p1.0 01001 p1.1 p1.1 01010 p1.2 p1.2 01011 p1.3 p1.3 01100 p1.4 reserved. 01101 p1.5 reserved. 01110 p1.6 reserved. 01111 p1.7 reserved. 10000: temp sensor temp sensor 10001: vreg output vreg output 10010: vdd vdd 10011: gnd gnd 10100 ? 11111: no input selected c8051f80x-83x 58 rev. 1.0 9. temperature sensor an on-chip temperature sensor is included on the c8051f800/1/2/3/4/5, c8051f812/3/4/5/6/7, c8051f824/5/6, and c8051f830/1/2 which can be dire ctly accessed via the adc multiplexer in single- ended configuration. to use the adc to measure th e temperature sensor, the adc mux channel should be configured to connect to the temperature sensor. the temperature sensor transfer function is shown in figure 9.1. the output voltage (v temp ) is the positive adc input when th e adc multiplexer is set correctly. the tempe bit in register ref0cn enables/disables the temperature sensor, as described in sfr defini- tion 10.1. while disabled, the temperature sensor defaults to a high impedance state and any adc mea- surements performed on the sensor will result in meaningless data. refer to table 7.11 for the slope and offset parameters of the temperature sensor. figure 9.1. temperature sensor transfer function 9.1. calibration the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea- surements (see table 5.1 for linearity specificati ons). for absolute temperature measurements, offset and/or gain calibration is recommended. typically a 1-po int (offset) calibration incl udes the following steps: 1. control/measure the ambient temperatur e (this temperature must be known). 2. power the device, and delay for a few seconds to allow for self-heating. 3. perform an adc conversion with the temperat ure sensor selected as the adc?s input. 4. calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent temperature sensor measurements. figure 5.3 shows the typical tem perature sensor error assuming a 1-point calibration at 0 c. parameters that affect adc measurem ent, in particular the voltage refer ence value, will also affect temper- ature measurement. temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope rev. 1.0 59 c8051f80x-83x figure 9.2. temperature sensor error with 1-point calibration at 0 c -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 c8051f80x-83x 60 rev. 1.0 10. voltage and ground reference options the voltage reference mux is configurable to use an externally connected voltage reference, the on-chip voltage reference, or one of two power supply voltages (see figure 10.1). the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedi- cated to analog ground (p0.1/agnd). the voltage and ground reference options are configured using the ref0cn sfr described on page 62. electrical specifications are can be found in the electrical specifications chapter. important note about the v ref and agnd inputs: port pins are used as the external v ref and agnd inputs. when using an external voltage reference, p0 .0/vref should be configured as an analog input and skipped by the digital crossbar. when using agnd as the ground reference to adc0, p0.1/agnd should be configured as an analog input and skipped by the digital crossbar. refer to section ?23. port input/out- put? on page 138 for complete port i/o configuration de tails. the external reference voltage must be within the range 0 ? v ref ? v dd and the external ground reference must be at the same dc voltage potential as gnd. figure 10.1. voltage reference functional block diagram p0.0/vref r1 vdd external voltage reference circuit gnd 00 01 10 11 ref0cn refsl0 tempe biase refsl1 refgnd recommended bypass capacitors + 4.7 ? f0.1 ? f internal 1.8v regulated digital supply v dd internal 1.65v high speed reference gnd p0.1/agnd refgnd 0 1 to analog mux temp sensor en bias generator to adc, internal oscillator, reference, tempsensor en ioscen rev. 1.0 61 c8051f80x-83x 10.1. external voltage references to use an external voltage refer ence, refsl[1:0] should be set to 00. bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. 10.2. internal voltage reference options a 1.65 v high-speed reference is included on-chip. the hi gh speed internal reference is selected by setting refsl[1:0] to 11. when se lected, the high speed internal refere nce will be automatically enabled on an as-needed basis by adc0. for applications with a non-varying power supply voltag e, using the power supply as the voltage reference can provide adc0 with added dynamic range at the cost of reduced power supply noise rejection. to use the 1.8 to 3.6 v power supply voltage (v dd ) or the 1.8 v regulated digital supply voltage as the reference source, refsl[1:0] should be set to 01 or 10, respectively. 10.3. analog ground reference to prevent ground noise generated by switching digi tal logic from affecting sensitive analog measure- ments, a separate analog ground reference option is available. when enabled, the ground reference for adc0 is taken from the p0.1/agnd pin. any external sensors sampled by adc0 should be referenced to the p0.1/agnd pin. the separate analog ground re ference option is enabled by setting refgnd to 1. note that when using this option, p0.1/agnd mu st be connected to the same potential as gnd. 10.4. temperature sensor enable the tempe bit in register ref0cn enables the temper ature sensor. while disabled, the temperature sen- sor defaults to a high impedance state and any adc0 measurements performed on the sensor result in meaningless data. c8051f80x-83x 62 rev. 1.0 sfr address = 0xd1 sfr definition 10.1. ref0cn: voltage reference control bit76543210 name refgnd refsl tempe biase type r r r/w r/w r/w r/w r/w r reset 00010000 bit name function 7:6 unused read = 00b; write = don?t care. 5refgnd analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the p0.1/agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the p0.0/vref pin. 01: the adc0 voltage reference is the vdd pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal 1.65 v high speed voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 unused read = 0b; write = don?t care. rev. 1.0 63 c8051f80x-83x 11. voltage regulator (reg0) c8051f80x-83x devices include an internal voltage regu lator (reg0) to regulate the internal core supply to 1.8 v from a v dd supply of 1.8 to 3.6 v. a power-saving mode is built into the regulator to help reduce current consumption in low-power applications. this mode is accessed through the reg0cn register (sfr definition 11.1). electrical characteristics fo r the on-chip regulator are specified in table 7.5 on page 41 under default conditio ns, when the device enters stop mode the internal regulato r will remain on. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the internal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin or a full power cycle of the device are the only methods of generating a reset. c8051f80x-83x 64 rev. 1.0 sfr address = 0xc9 sfr definition 11.1. reg0cn: voltage regulator control bit76543210 name stopcf type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7stopcf stop mode configuration. this bit configures the regulator?s be havior when the device enters stop mode. 0: regulator is still active in stop m ode. any enabled reset source will reset the device. 1: regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 6:0 reserved must write to 0000000b. rev. 1.0 65 c8051f80x-83x 12. comparator0 c8051f80x-83x devices include an on-chip progra mmable voltage comparator, comparator0, shown in figure 12.1. the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally availabl e at the port pins: a synchronous ?latched? output (cp0), or an asyn- chronous ?raw? output (cp0a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outpu t may be configured as open drain or push-pull (see section ?23.4. port i/o initialization? on page 147). comparator0 may also be used as a reset source (see section ?21.5. comparator0 reset? on page 127). the comparator0 inputs are selected by the comparator input multiplexer, as detailed in section ?12.1. comparator multiplexer? on page 69. figure 12.1. comparator0 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the co mparator output is available asyn chronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the compar ator is turned off. see section ?23.3. priority crossbar decoder? on page 143 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in section ?7. electrical characteristics? on page 39. vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 c8051f80x-83x 66 rev. 1.0 the comparator response time may be configured in software via the cpt0md register (see sfr defini- tion 12.2). selecting a longer response time reduces the comparator supply current. figure 12.2. comparator hysteresis plot the comparator hysteresis is software-programmabl e via its comparator cont rol register cpt0cn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmed using bits 3 : 0 in the comparator control register cpt0cn (shown in sfr definition 12.1). the amount of negative hysteresis voltage is determined by the settings of the cp0hyn bits. as shown in figure 12.2, settings of 20, 10 or 5 mv of negative hysteresis can be pro- grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see section ?18.1. mcu interrupt sources and vectors? on page 103). the cp0fif flag is set to logic 1 upon a comparator falling-edge occurrence, and the cp0rif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft- ware. the comparator rising-edge interrupt mask is enabled by setting cp0rie to a logic 1. the comparator0 falling-edge interrupt mask is enabled by setting cp0fie to a logic 1. the output state of the comparator can be obtained at any time by reading the cp0out bit. the compar- ator is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is first powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol rev. 1.0 67 c8051f80x-83x sfr address = 0x9b sfr definition 12.1. cpt0 cn: comparator0 control bit76543210 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. c8051f80x-83x 68 rev. 1.0 sfr address = 0x9d sfr definition 12.2. cpt0md: comparator0 mode selection bit76543210 name cp0rie cp0fie cp0md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused read = 00b, write = don?t care. 5cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption) rev. 1.0 69 c8051f80x-83x 12.1. comparator multiplexer c8051f80x-83x devices include an analog input multip lexer to connect port i/o pins to the comparator inputs. the comparator0 inputs are selected in the cpt0mx register (sfr definition 12.3). the cmx0p3 ? cmx0p0 bits select the comparator0 positive input; the cmx0n3 ? cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be configured as analog inputs in their associ ated port configuration register, and configured to be skipped by the crossbar (for details on port configur ation, see section ?23.6. special function registers for accessing and configuring port i/o? on page 152). figure 12.3. comparator input multiplexer block diagram + - cp0 + cp0 - cpt0mx cmx0p0 cmx0p1 cmx0p2 cmx0p3 cmx0n3 cmx0n2 cmx0n1 cmx0n0 gnd vdd p0.0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 vreg output p0.1 p0.3 p0.5 p0.7 p1.1 p1.3 p1.5 p1.7 vreg output note: p1.4-p1.7 are not available on the 16-pin packages. c8051f80x-83x 70 rev. 1.0 sfr address = 0x9f sfr definition 12.3. cpt0mx: comparator0 mux selection bit76543210 name cmx0n[3:0] cmx0p[3:0] type r/w r/w reset 11111111 bit name function 7:4 cmx0n[3:0] comparator0 negative input mux selection. 20-pin and 24-pin devices 16-pin devices 0000 p0.1 p0.1 0001 p0.3 p0.3 0010 p0.5 p0.5 0011 p0.7 p0.7 0100 p1.1 p1.1 0101 p1.3 p1.3 0110 p1.5 reserved. 0111 p1.7 reserved. 1000 vreg output. vreg output. 1001?1111 no input selected. no input selected. 3:0 cmx0p[3:0] comparator0 positive input mux selection. 20-pin and 24-pin devices 16-pin devices 0000 p0.0 p0.0 0001 p0.2 p0.2 0010 p0.4 p0.4 0011 p0.6 p0.6 0100 p1.0 p1.0 0101 p1.2 p1.2 0110 p1.4 reserved. 0111 p1.6 reserved. 1000 vreg output. vreg output. 1001?1111 no input selected. no input selected. rev. 1.0 71 c8051f80x-83x 13. capacitive sense (cs0) the capacitive sense subsystem included on the c8051f800/1/3/4/6/7/9, c8051f810/2/3/5/6/8/9, c8051f821/2/4/5/7/8, c8051f830/1/3/4 uses a capacitanc e-to-digital circuit to determine the capacitance on a port pin. the module can take measurements from different port pins using the module?s analog mul- tiplexer. the multiplexer supports up to 16 channels. see sfr definition 13.9. ?cs0mx: capacitive sense mux channel select? on page 81 for cha nnel availability for specific part numbers. the module is enabled only when the cs0en bit (cs0cn) is set to 1. otherwis e the module is in a low-power shutdown state. the module can be configured to take measurements on on e port pin or a group of port pins, using auto-scan. an accumulator can be configured to accumulate multiple conversions on an input channel. interrupts can be generated when cs0 completes a conversion or when the measured value crosses a threshold defined in cs0thh:l. figure 13.1. cs0 block diagram 16-bit capacitance to digital converter timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 cs0busy (w) cs0cmpf 001 010 011 100 reserved greater than compare logic 101 initiated continuously cs0thh:l cs0dh:l auto-scan logic cs0ss cs0se cs0mx 22-bit accumulator 110 111 initiated continuously when auto-scan enabled reserved cs0cn cs0cmpf cs0cmpen cs0busy cs0int cs0en cs0cf cs0acu0 cs0acu1 cs0acu2 cs0cm0 cs0cm1 cs0cm2 amux . . . c8051f80x-83x 72 rev. 1.0 13.1. configuring port pi ns as capacitive sense inputs in order for a port pin to be measured by cs0, that port pin must be configured as an analog input (see ?23. port input/output ? ). configuring the input mult iplexer to a port pin not conf igured as an analog input will cause the capacitive sense comparator to output incorrect measurements. 13.2. capacitive sense start-of-conversion sources a capacitive sense conversion can be initiated in one of seven ways, depending on the programmed state of the cs0 start of conversion bits (cs0cf6:4). co nversions may be initiated by one of the following: 1. writing a 1 to the cs0busy bit of register cs0cn 2. timer 0 overflow 3. timer 2 overflow 4. timer 1 overflow 5. convert continuously 6. convert continuously with auto-scan enabled conversions can be configured to be initiated cont inuously through one of two methods. cs0 can be con- figured to convert at a single channel continuously or it can be configured to convert continuously with auto-scan enabled. when configured to convert continuously, conver sions will begin after the cs0busy bit in cs0cf has been set. an interrupt will be genera ted if cs0 conversion complete interrup ts are enabled by setting the ecscpt bit (eie2.0). note: cs0 conversion complete interrupt behavior depends on the settings of the cs0 accumulator. if cs0 is configured to accumulate multiple conversions on an input channel, a cs0 conversion complete interrupt will be generated only after the last conversion completes. 13.3. automatic scanning cs0 can be configured to automatically scan a sequenc e of contiguous cs0 input channels by configuring and enabling auto-scan. using auto-scan with the cs 0 comparator interrupt enabled allows a system to detect a change in measured capacitance without requiring any additional dedicated mcu resources. auto-scan is enabled by setting the cs0 start-of-con version bits (cs0cf6:4) to 111b. after enabling auto- scan, the starting and ending channels should be set to appropriate values in cs0ss and cs0se, respec- tively. writing to cs0ss when auto- scan is enabled will cause the value wr itten to cs0ss to be copied into cs0mx. after being enabled, writ ing a 1 to cs0busy will start auto-sc an conversions. when auto-scan completes the number of conversions defined in the cs0 accumulator bits (cs0cf1:0) (see ?13.5. cs0 conversion accumulator? ), auto-scan configures cs 0mx to the next highest po rt pin configured as an analog input and begins a conver sion on that channel. this scan sequence continues until cs0mx reaches the ending input channel val ue defined in cs0se. after one or more conversions have been taken at this channel, auto-scan configures cs0mx back to the starting input chan nel. for an example system configured to use auto-scan, please see fi gure ?13.2 auto-scan example? on page 73. note: auto-scan attempts one conversion on a cs0mx channel regardless of whether that channel?s port pin has been configured as an analog input. if auto-scan is enable d when the device enters su spend mode, auto-scan will re main enabled and running. this feature allows the device to wake from susp end through cs0 greater-than comparator event on any configured capacitive sense input included in the auto-scan sequence of inputs. rev. 1.0 73 c8051f80x-83x figure 13.2. auto-scan example 13.4. cs0 comparator the cs0 comparator compares the latest capacitive sense conversion result with the value stored in cs0thh:cs0thl. if the result is less than or equal to the stored value, the cs0cmpf bit(cs0cn:0) is set to 0. if the result is greater than the stored value, cs0cmpf is set to 1. if the cs0 conversion accumulator is configured to accumula te multiple conversion s, a comparison will not be made until the last conversion has been accumulated. an interrupt will be gene rated if cs0 greater-than comparator in terrupts are enabled by setting the ecs- grt bit (eie2.1) when the comparator sets cs0cmpf to 1. if auto-scan is running when the comparator sets the cs0cmpf bit, no further auto-scan initiated conver- sions will start until firmware sets cs0busy to 1. a cs0 greater-than comparator event can wake a device from suspend mode. this feature is useful in sys- tems configured to continuously sa mple one or more capacitive sens e channels. the device will remain in the low-power suspend state until the captured va lue of one of the scanned channels causes a cs0 greater-than comparator event to occur. it is not necessary to have cs0 comparator interrupts enabled in order to wake a device from suspend with a greater-than event. note: on waking from suspend mode due to a cs0 grea ter-than comparator event, the cs0cn register should be accessed only after at least two system clock cycles have elapsed. for a summary of behavior with different cs0 comp arator, auto-scan, and auto accumulator settings, please see table 13.1. sfr configuration: a d a a d d d d d a a a a a a a p0.0 . . . pxmdin bit port pin 0 cs0mx channel p0.1 1 p0.2 2 p0.3 3 p0.4 4 p0.5 5 p0.6 6 p0.7 7 p1.0 8 p1.1 9 p1.2 10 p1.3 11 p1.4 12 p1.5 13 p1.6 14 p1.7 15 cs0ss = 0x02 cs0se = 0x0d p0mdin = 0xf2 p1mdin = 0x04 cs0cf = 0x70 cs0cn = 0x80 enables capsense0 enables auto-scan as start-of- conversion source sets p0.2 as auto- scan starting channel sets p1.5 as auto- scan ending channel configures p0.3, p0.2, p0.0 as analog inputs configures p1.0-p1.1 and p1.3-p1.7 as analog inputs scans on channels not configured as analog inputs result in indeterminate values that cannot trigger a cs0 greater than interrupt event c8051f80x-83x 74 rev. 1.0 13.5. cs0 conversion accumulator cs0 can be configured to accumulate multiple conversi ons on an input channel. the number of samples to be accumulated is configured using the cs0acu2:0 bi ts (cs0cf2:0). the accumulator can accumulate 1, 4, 8, 16, 32, or 64 samples. after the defined number of samples have been accumulated, the result is con- verted to a 16-bit value by dividing the 22-bit accumulator by either 1, 4, 8, 16, 32, or 64 (depending on the cs0acu[2:0] setting) and copied to the cs0dh:cs0dl sfrs. table 13.1. operation with auto-scan and accumulate auto-scan enabled accumulator enabled cs0 conversion complete interrupt behavior cs0 greater than interrupt behavior cs0mx behavior nn cs0int interrupt serviced after 1 conversion com- pletes interrupt serviced after 1 con- version complete s if value in cs0dh:cs0dl is greater than cs0thh:cs0thl cs0mx unchanged. ny cs0int interrupt serviced after m conversions com- plete interrupt serviced after m con- versions complete if value in 16-bit accumulator is greater than cs0thh:cs0thl cs0mx unchanged. yn cs0int interrupt serviced after 1 conversion com- pletes interrupt serviced after con- version complete s if value in cs0dh:cs0dl is greater than cs0thh:cs0thl; auto-scan stopped if greater-than comparator detects conver- sion value is greater than cs0thh:cs0thl, cmux0 is left unchanged; otherwise, cmux0 updates to the next channel (cs0mx + 1) and wraps back to cs0ss after passing cs0se yy cs0int interrupt serviced after m conversions com- plete interrupt serviced after m con- versions complete if value in 16-bit accumulator is greater than cs0thh:cs0thl; auto- scan stopped if greater-than comparator detects conver- sion value is greater than cs0thh:cs0thl, cs0mx is left unchanged; otherwise, cs0mx updates to the next channel (cs0mx + 1) and wraps back to cs0ss after passing cs0se m = accumulator setting (1x, 4x, 8x, 16x, 32x, 64x) rev. 1.0 75 c8051f80x-83x sfr address = 0xb0; bit-addressable sfr definition 13.1. cs0cn: capacitive sense control bit7654 3 210 name cs0en cs0int cs0busy cs0cmpen cs0cmpf type r/w r r/w r/w r/w r r r reset 0000 0 000 bit name description 7cs0en cs0 enable. 0: cs0 disabled and in low-power mode. 1: cs0 enabled and ready to convert. 6unused read = 0b; write = don?t care 5cs0int cs0 interrupt flag. 0: cs0 has not completed a data conversion since the last time cs0int was cleared. 1: cs0 has completed a data conversion. this bit is not automatically cleared by hardware. 4 cs0busy cs0 busy. read: 0: cs0 conversion is complete or a conversion is not currently in progress. 1: cs0 conversion is in progress. write: 0: no effect. 1: initiates cs0 conversion if cs0cm[2:0] = 000b, 110b, or 111b. 3 cs0cmpen cs0 digital comparator enable bit. enables the digital comparator, which compares accumulated cs0 conversion output to the value stored in cs0thh:cs0thl. 0: cs0 digital comparator disabled. 1: cs0 digital comparator enabled. 2:1 unused read = 00b; write = don?t care 0 cs0cmpf cs0 digital comparator interrupt flag. 0: cs0 result is smaller than the value set by cs0thh and cs0thl since the last time cs0cmpf was cleared. 1: cs0 result is greater than the value set by cs0thh and cs0thl since the last time cs0cmpf was cleared. note: on waking from suspend mode due to a cs0 grea ter-than comparator event, the cs0cn register should be accessed only after at least two system clock cycles have elapsed. c8051f80x-83x 76 rev. 1.0 sfr address = 0x9e sfr definition 13.2. cs0cf: ca pacitive sense configuration bit76543210 name cs0cm[2:0] cs0acu[2:0] type r r/w r/w r/w r r/w r/w r/w reset 00000000 bit name description 7 unused read = 0b; write = don?t care 6:4 cs0cm[2:0] cs0 start of conversion mode select. 000: conversion initiated on ev ery write of 1 to cs0busy. 001: conversion initiated on overflow of timer 0. 010: conversion initiated on overflow of timer 2. 011: conversion initiated on overflow of timer 1. 100: reserved. 101: reserved. 110: conversion initiated continuously after writing 1 to cs0busy. 111: auto-scan enabled, conversions init iated continuously after writing 1 to cs0busy. 3 unused read = 0b; write = don?t care 2:0 cs0acu[2:0] cs0 accumulator mode select. 000: accumulate 1 sample. 001: accumulate 4 samples. 010: accumulate 8 samples. 011: accumulate 16 samples 100: accumulate 32 samples. 101: accumulate 64 samples. 11x: reserved. rev. 1.0 77 c8051f80x-83x sfr address = 0xac sfr address = 0xab sfr definition 13.3. cs0dh: capa citive sense data high byte bit76543210 name cs0dh[7:0] type rrrrrrrr reset 00000000 bit name description 7:0 cs0dh cs0 data high byte. stores the high byte of the last comp leted 16-bit capacitive sense conversion. sfr definition 13.4. cs0dl: ca pacitive sense data low byte bit76543210 name cs0dl[7:0] type rrrrrrrr reset 00000000 bit name description 7:0 cs0dl cs0 data low byte. stores the low byte of the last comple ted 16-bit capacitive sense conversion. c8051f80x-83x 78 rev. 1.0 sfr address = 0xb9 sfr address = 0xba sfr definition 13.5. cs0ss: capaciti ve sense auto-scan start channel bit76543210 name cs0ss[4:0] type r r r r/w r/w r/w r/w r/w reset 00000000 bit name description 7:5 unused read = 000b; write = don?t care 4:0 cs0ss[4:0] starting channel for auto-scan. sets the first cs0 channel to be selected by the mux for capacitive sense conver- sion when auto-scan is enabled and active. when auto-scan is enabled, a writ e to cs0ss will also update cs0mx. sfr definition 13.6. cs0se: capaciti ve sense auto-scan end channel bit76543210 name cs0se[4:0] type r r r r/w r/w r/w r/w r/w reset 00000000 bit name description 7:5 unused read = 000b; write = don?t care 4:0 cs0se[4:0] ending channel for auto-scan. sets the last cs0 channel to be selected by the mux for capacitive sense conver- sion when auto-scan is enabled and active. rev. 1.0 79 c8051f80x-83x sfr address = 0x97 sfr address = 0x96 sfr definition 13.7. cs0thh: capacitive sense comparator threshold high byte bit76543210 name cs0thh[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description 7:0 cs0thh[7:0] cs0 comparator threshold high byte. high byte of the 16-bit value compared to the capacitive sense conversion result. sfr definition 13.8. cs0thl: capacitive sense comparator threshold low byte bit76543210 name cs0thl[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description 7:0 cs0thl[7:0] cs0 comparator threshold low byte. low byte of the 16-bit value compared to the capacitive sense conversion result. c8051f80x-83x 80 rev. 1.0 13.6. capacitive sense multiplexer the input multiplexer can be controlled through two methods. the cs0mx register can be written to through firmware, or the register can be configured automatically using the modu les auto-scan functionality (see ?13.3. automatic scanning? ). figure 13.3. cs0 multiplexer block diagram capsense0 cs0mux cs0mx cs0uc cs0mx3 cs0mx2 cs0mx1 cs0mx0 p0.0 p1.7 (up to 16 channels) note: see the cs0mx sfr definition for channel availab ility for specific part numbers. rev. 1.0 81 c8051f80x-83x sfr address = 0x9c sfr definition 13.9. cs0mx: capaci tive sense mux channel select bit76543210 name cs0uc cs0mx[3:0] type r/w r r r r/w r/w r/w r/w reset 10011111 bit name description 7cs0uc cs0 unconnected. disconnects cs0 from all port pins, regardless of the selected channel. 0: cs0 connected to port pins 1: cs0 disconnected from port pins 6:4 reserved read = 000b; write = 000b 3:0 cs0mx[3:0] cs0 mux channel select. selects one of the 16 input channel s for capacitive sense conversion. value c8051f800/6, c8051f812/8 c8051f803/9, c8051f815, c8051f821/4/7, c8051f830/3 c8051f801/4/7, c8051f810/3/6/9, c8051f822/5/8, c8051f831/4 0000 p0.0 p0.0 p0.0 0001 p0.1 p0.1 p0.1 0010 p0.2 p0.2 p0.2 0011 p0.3 p0.3 p0.3 0100 p0.4 p0.4 p0.4 0101 p0.5 p0.5 p0.5 0110 p0.6 p0.6 p0.6 0111 p0.7 p0.7 p0.7 1000 p1.0 p1.0 reserved. 1001 p1.1 p1.1 reserved. 1010 p1.2 p1.2 reserved. 1011 p1.3 p1.3 reserved. 1100 p1.4 reserved. reserved. 1101 p1.5 reserved. reserved. 1110 p1.6 reserved. reserved. 1111 p1.7 reserved. reserved. note: cs0mx is reserved on all the devices that are not listed in the above table. c8051f80x-83x 82 rev. 1.0 14. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see descriptio n in section 30), and interfaces directly with the ana- log and digital subsystems providing a complete data acqu isition or control-system so lution in a single inte- grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 14.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except fo r mul and div take 12 or 24 system clock cycles to execute, and usually have a maximu m system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 14.1. cip-51 block diagram ?? fully compatible with mcs-51 instruction set ?? 25 mips peak throughput with 25 mhz clock ?? 0 to 25 mhz clock frequency ?? extended interrupt handler ?? reset input ?? power management modes ?? on-chip debug logic ?? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8 rev. 1.0 83 c8051f80x-83x with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. 14.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 14.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as o pposed to when the branch is taken. table 14.1 is the cip-51 instruction set summary, which includes the mnemonic, number of byte s, and number of clock cycles for each instruction. clocks to execute 1 22/333/444/55 8 number of instructions 26 50 5 14 6 3 2 2 1 c8051f80x-83x 84 rev. 1.0 table 14.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 rev. 1.0 85 c8051f80x-83x xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 table 14.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles c8051f80x-83x 86 rev. 1.0 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 33/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/5 djnz rn, rel decrement regist er and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 14.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles rev. 1.0 87 c8051f80x-83x notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to the first byte of the follo wing instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall a nd ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. c8051f80x-83x 88 rev. 1.0 14.2. cip-51 re gister descriptions following are descriptions of sfrs related to the opera tion of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implem ent new features in which ca se the reset value of the bi t will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the data sheet associated wit h their corresponding system function. sfr address = 0x82 sfr address = 0x83 sfr definition 14.1. dpl: data pointer low byte bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 14.2. dph: data pointer high byte bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. rev. 1.0 89 c8051f80x-83x sfr address = 0x81 sfr address = 0xe0; bit-addressable sfr definition 14.3. sp: stack pointer bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre- mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 14.4. acc: accumulator bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. c8051f80x-83x 90 rev. 1.0 sfr address = 0xf0; bit-addressable sfr definition 14.5. b: b register bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations. rev. 1.0 91 c8051f80x-83x sfr address = 0xd0; bit-addressable sfr definition 14.6. psw: program status word bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor- row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith- metic operations. 5f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: ?? an add, addc, or subb instruction causes a sign-change overflow. ?? a mul instruction results in an overflow (result is greater than 255). ?? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even. c8051f80x-83x 92 rev. 1.0 15. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f80x-83x device family is shown in figure 15.1 figure 15.1. c8051f80x-83x memory map program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 256 bytes (accessable using movx instruction) 0x0000 0x00ff same 256 bytes as from 0x0000 to 0x01ff, wrapped on 256-byte boundaries 0x0100 0xffff 16 kb flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x3fff 0x3ffe c8051f80x and c8051f810/1 8 kb flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x1fff 0x1ffe c8051f812/3/4/5/6/7/8/9 and c8051f82x 4 kb flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x0fff 0x0ffe c8051f830/1/2/3/4/5 c8051f80x, c8051f81x, and c8051f820/1/2/3 only rev. 1.0 93 c8051f80x-83x 15.1. program memory the members of the c8051f80x-83x device family contain 16 kb (c8051f80x and c8051f810/1), 8 kb (c8051f812/3/4/5/6/7/8/9 and c8051f82x), or 4 kb (c8051f830/1/2/3/4/5) of re-programmable flash memory that can be used as non-volatile program or data storage. the last by te of user code space is used as the security lock byte (0x3fff on 16 kb devices, 0x1fff on 8 kb devices and 0x0fff on 4 kb devices). figure 15.2. flash program memory map 15.1.1. movx instructio n and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f80x-83x devices, the movx in struction is normally used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash me mory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase an d write flash. this flash access feature provides a mechanism for the c8051f80x-83x to update program code and use the program mem- ory space for non-volatile data storage. refer to section ?19. flash memory? on page 113 for further details. 15.2. data memory the members of the c8051f80x-83x device family contain 512 bytes (c8051f80x, c8051f81x, and c8051f820/1/2/3) or 256 bytes (c8051f824/5/6/7/8/9 and c8051f830/1/2/3/4/5) of ram data memory. for all c8051f80x-83x devices, 256 bytes of this memo ry is mapped into the internal ram space of the 8051. for the devices with 512 bytes of ram, the remain ing 256 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 15.1 for reference. 15.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x 20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines lock byte 0x0000 0x3fff 0x3ffe flash memory organized in 512-byte pages 0x3e00 flash memory space lock byte page lock byte 0x0000 0x1fff 0x1ffe 0x1e00 flash memory space lock byte page lock byte 0x0000 0x0fff 0x0ffe 0x0e00 flash memory space lock byte page c8051f80x and c8051f810/1 (16kb) c8051f812/3/4/5/6/7/8/9 and c8051f82x (8 kb) c8051f830/1/2/3/4/5 (4 kb) c8051f80x-83x 94 rev. 1.0 whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 15.1 illustra tes the data memory organiz ation of the c8051f80x- 83x. 15.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of ei ght byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see desc ription of the psw in sfr definition 14.6). this allows fast context switching when entering subroutines and in terrupt service routines. in direct addressing modes use registers r0 and r1 as index registers. 15.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 15.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes t he stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis- ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. rev. 1.0 95 c8051f80x-83x 16. in-system device identification the c8051f80x-83x has sfrs that identify the device family and derivative. these sfrs can be read by firmware at runtime to determine th e capabilities of the mcu that is ex ecuting code. this allows the same firmware image to run on mcus with different memory sizes and peripherals, and dynamically changing functionality to suit the capabilities of that mcu. in order for firmware to identify the mcu, it must read three sfrs. hwid describes the mcu?s family, derivid describes the specific der ivative within that device family , and revid describes the hardware revision of the mcu. sfr address = 0xb5 sfr definition 16.1. hwid: ha rdware identification byte bit76543210 name hwid[7:0] type rrrrrrrr reset 00100011 bit name description 7:0 hwid[7:0] hardware identification byte. describes the mcu family. 0x23: devices covered in this document (c8051f80x-83x) c8051f80x-83x 96 rev. 1.0 sfr address = 0xad sfr address = 0xb6 sfr definition 16.2. derivid: derivative iden tification byte bit76543210 name derivid[7:0] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name description 7:0 derivid[7:0] derivative identification byte. shows the c8051f80x-83x derivative being used. 0xd0: c8051f800; 0xd1: c8051f801; 0xd2: c8051f802; 0xd3: c8051f803 0xd4: c8051f804; 0xd5: c8051f805; 0xd6: c8051f806; 0xd7: c8051f807 0xd8: c8051f808; 0xd9: c8051f809; 0xda: c8051f810; 0xdb: c8051f811 0xdc: c8051f812; 0xdd: c8051f813; 0xde: c8051f814; 0xdf: c8051f815 0xe0: c8051f816; 0xe1: c8051f817; 0xe2: c8051f818; 0xe3: c8051f819 0xe4: c8051f820; 0xe5: c8051f821; 0xe6: c8051f822; 0xe7: c8051f823 0xe8: c8051f824; 0xe9: c8051f825; 0xea: c8051f826; 0xeb: c8051f827 0xec: c8051f828; 0xed: c8051f829; 0xee: c8051f830; 0xef: c8051f831 0xf0: c8051f832; 0xf1: c8051f833; 0xf2: c8051f834; 0xf3: c8051f835 sfr definition 16.3. revid: hardwa re revision iden tification byte bit76543210 name revid[7:0] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name description 7:0 revid[7:0] hardware revision identification byte. shows the c8051f80x-83x hardware revision being used. for example, 0x00 = revision a. rev. 1.0 97 c8051f80x-83x 17. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the c8051f80x-83x's resources and peripher- als. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the c8051f80x- 83x. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruc- tion set. table 17.1 lists the sfrs implemented in the c8051f80x-83x device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all ot her sfrs are byte-addressable only. unoccupied addresses in the sfr space are rese rved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in table 17.2, for a detailed description of each register. table 17.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 p0mat p0mask vdm0cn f0 b p0mdin p1mdin eip1 eip2 pca0pwm e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 p1mat p1mask rstsrc e0 acc xbr0 xbr1 it01cf eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cp m1 pca0cpm2 crc0in crc0data d0 psw ref0cn crc0auto crc0cnt p0skip p1skip smb0adm smb0adr c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h crc0cn crc0flip c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth b8 ip cs0ss cs0se adc0mx adc0cf adc0l adc0h b0 cs0cn oscxcn oscicn oscicl hwid revid flkey a8 ie clksel cs0dl cs0dh dervid a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout 98 scon0 sbuf0 cpt0cn cs0mx cpt0md cs0cf cpt0mx 90 p1 cs0thl cs0thh 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) note: sfr addresses ending in 0x0 or 0x8 are bit-addressable locations, and can be used with bitwise instructions. c8051f80x-83x 98 rev. 1.0 table 17.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 89 adc0cf 0xbc adc0 configuration 50 adc0cn 0xe8 adc0 control 52 adc0gth 0xc4 adc0 greater-than compare high 53 adc0gtl 0xc3 adc0 greater-than compare low 53 adc0h 0xbe adc0 high 51 adc0l 0xbd adc0 low 51 adc0lth 0xc6 adc0 less-than compare word high 54 adc0ltl 0xc5 adc0 less-than compare word low 54 adc0mx 0xbb amux0 multiplexer channel select 57 b 0xf0 b register 90 ckcon 0x8e clock control 210 clksel 0xa9 clock select 210 cpt0cn 0x9b comparator0 control 67 cpt0md 0x9d comparator0 mode selection 68 cpt0mx 0x9f comparator0 mux selection 70 crc0auto 0xd2 crc0 automatic control register 165 crc0cn 0xce crc0 control 163 crc0cnt 0xd3 crc0 automatic fl ash sector count 165 crc0data 0xde crc0 data output 164 crc0flip 0xcf crc0 bit flip 166 crc0in 0xdd crc data input 164 cs0thh 0x97 cs0 digital compare threshold high 79 cs0thl 0x96 cs0 digital compare threshold high 79 cs0cn 0xb0 cs0 control 75 cs0dh 0xac cs0 data high 77 cs0dl 0xab cs0 data low 77 rev. 1.0 99 c8051f80x-83x cs0cf 0x9e cs0 configuration 76 cs0mx 0x9c cs0 mux 81 cs0se 0xba auto scan end channel 78 cs0ss 0xb9 auto scan start channel 78 derivid 0xad derivative identification 96 dph 0x83 data pointer high 88 dpl 0x82 data pointer low 88 eie1 0xe6 extended interrupt enable 1 107 eie2 0xe7 extended interrupt enable 2 108 eip1 0xf3 extended interrupt priority 1 109 eip2 0xf4 extended interrupt priority 2 110 flkey 0xb7 flash lock and key 119 hwid 0xb5 hardware identification 95 ie 0xa8 interrupt enable 105 ip 0xb8 interrupt priority 106 it01cf 0xe4 int0/int1 configuration 112 oscicl 0xb3 internal oscilla tor calibration 131 oscicn 0xb2 internal oscillator control 132 oscxcn 0xb1 external oscillator control 134 p0 0x80 port 0 latch 153 p0mask 0xfe port 0 mask 151 p0mat 0xfd port 0 match 151 p0mdin 0xf1 port 0 input mode configuration 154 p0mdout 0xa4 port 0 output mode configuration 154 p0skip 0xd4 port 0 skip 155 p1 0x90 port 1 latch 155 p1mask 0xee p0 mask 152 table 17.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page c8051f80x-83x 100 rev. 1.0 p1mat 0xed p1 match 152 p1mdin 0xf2 port 1 input mode configuration 156 p1mdout 0xa5 port 1 output mode configuration 156 p1skip 0xd5 port 1 skip 157 p2 0xa0 port 2 latch 157 p2mdout 0xa6 port 2 output mode configuration 158 pca0cn 0xd8 pca control 238 pca0cph0 0xfc pca capture 0 high 243 pca0cph1 0xea pca capture 1 high 243 pca0cph2 0xec pca capture 2 high 243 pca0cpl0 0xfb pca capture 0 low 243 pca0cpl1 0xe9 pca capture 1 low 243 pca0cpl2 0xeb pca capture 2 low 243 pca0cpm0 0xda pca module 0 mode register 241 pca0cpm1 0xdb pca module 1 mode register 241 pca0cpm2 0xdc pca module 2 mode register 241 pca0h 0xfa pca counter high 242 pca0l 0xf9 pca counter low 242 pca0md 0xd9 pca mode 239 pca0pwm 0xf7 pca pwm configuration 240 pcon 0x87 power control 122 psctl 0x8f program store r/w control 118 psw 0xd0 program status word 91 ref0cn 0xd1 voltage reference control 62 reg0cn 0xc9 voltage regulator control 64 revid 0xb6 revision id 96 rstsrc 0xef reset source configuration/status 128 table 17.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page rev. 1.0 101 c8051f80x-83x sbuf0 0x99 uart0 data buffer 207 scon0 0x98 uart0 control 206 smb0adm 0xd6 smbus slave address mask 191 smb0adr 0xd7 smbus slave address 191 smb0cf 0xc1 smbus configuration 186 smb0cn 0xc0 smbus control 188 smb0dat 0xc2 smbus data 192 sp 0x81 stack pointer 89 spi0cfg 0xa1 spi0 configuration 174 spi0ckr 0xa2 spi0 clock rate control 176 spi0cn 0xf8 spi0 control 175 spi0dat 0xa3 spi0 data 176 tcon 0x88 timer/counter control 215 th0 0x8c timer/counter 0 high 218 th1 0x8d timer/counter 1 high 218 tl0 0x8a timer/counter 0 low 217 tl1 0x8b timer/counter 1 low 217 tmod 0x89 timer/counter mode 216 tmr2cn 0xc8 timer/counter 2 control 222 tmr2h 0xcd timer/counter 2 high 224 tmr2l 0xcc timer/counter 2 low 224 tmr2rlh 0xcb timer/counter 2 reload high 223 tmr2rll 0xca timer/counter 2 reload low 223 vdm0cn 0xff vdd monitor control 126 xbr0 0xe1 port i/o crossbar control 0 148 xbr1 0xe2 port i/o crossbar control 1 149 all other sfr locations reserved table 17.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page c8051f80x-83x 102 rev. 1.0 18. interrupts the c8051f80x-83x includes an extended interrupt sy stem supporting a total of 15 interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the devi ce. each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr. when a pe ripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt re quest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (t he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie?eie1). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enabl es are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. rev. 1.0 103 c8051f80x-83x 18.1. mcu interrupt sources and vectors the c8051f80x-83x mcus support 15 interrupt sources. software can simulate an interrupt by setting an interrupt-pending flag to logic 1. if interrupts are enabled fo r the flag, an in terrupt request w ill be generated and the cpu will vector to the isr address associated wit h the interrupt- pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits are summarized in table 18.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s). 18.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pr eempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 18.1. 18.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrup t and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. c8051f80x-83x 104 rev. 1.0 18.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). table 18.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) pmat (eip1.1) adc0 window compare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) reserved reserved cs0 conversion com- plete 0x007b 15 cs0int (cs0cn.5) n n ecscpt (eie2.0) psccpt (eip2.0) cs0 greater than 0x0083 16 cs0cmpf (cs0cn.0) n n ecsgrt (eie2.1) pscgrt (eip2.1) rev. 1.0 105 c8051f80x-83x sfr address = 0xa8; bit-addressable sfr definition 18.1. ie: interrupt enable bit76543210 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it ov errides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. c8051f80x-83x 106 rev. 1.0 sfr address = 0xb8; bit-addressable sfr definition 18.2. ip: interrupt priority bit76543210 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level. rev. 1.0 107 c8051f80x-83x sfr address = 0xe6 sfr definition 18.3. eie1: ex tended interrupt enable 1 bit76543210 name reserved reserv ed ecp0 eadc0 epca0 ewadc0 emat esmb0 type w w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved must write 0. 6 reserved reserved. must write 0. 5ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 rising edge or falling edge interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif and cp0fif flags. 4 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 3 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 2ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 1emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. c8051f80x-83x 108 rev. 1.0 sfr address = 0xe7 sfr definition 18.4. eie2: ex tended interrupt enable 2 bit76543210 name ecsgrt ecscpt type rrrrrrr/wr/w reset 00000000 bit name function 7:2 unused read = 000000b; write = don?t care. 1ecsgrt enable capacitive sense greater than comparator interrupt. 0: disable capacitive sense greater than comparator interrupt. 1: enable interrupt requests generated by cs0cmpf. 0ecscpt enable capacitive sense conversion complete interrupt. 0: disable capacitive sense co nversion comple te interrupt. 1: enable interrupt requests generated by cs0int. rev. 1.0 109 c8051f80x-83x sfr address = 0xf3 sfr definition 18.5. eip1: extended interrupt priority 1 bit76543210 name reserved reserved pcp0 ppca0 padc0 pwadc0 pmat psmb0 type w w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 reserved must write 0. 5pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp 0 rising edge or falling edge interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. c8051f80x-83x 110 rev. 1.0 sfr address = 0xf4 sfr definition 18.6. eip2: extended interrupt priority 2 bit76543210 name reserved reserved reserved reserv ed reserved reserved pscgrt psccpt type rrrrrrr/wr/w reset 00000000 bit name function 7:2 reserved 1 pscgrt capacitive sense greater than comparator priority control. this bit sets the priority of the capaciti ve sense greater than comparator interrupt. 0: cs0 greater than comparator inte rrupt set to low priority level. 1: cs0 greater than comparator set to high priority level. 0 psccpt capacitive sense conversion complete priority control. this bit sets the priority of the capacitive sense conversion complete interrupt. 0: cs0 conversion complete set to low priority level. 1: cs0 conversion complete set to high priority level. rev. 1.0 111 c8051f80x-83x 18.3. int0 and int1 external interrupts the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?28.1. timer 0 and timer 1? on page 211) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 18.7). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?23.3. priority crossbar decoder? on page 143 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request bef ore execution of the isr completes or another interr upt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive c8051f80x-83x 112 rev. 1.0 sfr address = 0xe4 sfr definition 18.7. it01cf: int0 /int1 configuration bit76543210 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 00000001 bit name function 7in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 rev. 1.0 113 c8051f80x-83x 19. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx write instruction. once cleared to logic 0, a flash bit mu st be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before be ing reprogrammed. the write and erase operations are automatically timed by hard ware for proper execution; data polling to determine the end of th e write/erase operations is not required. code execution is st alled during flash write/erase operations. refer to table 7.6 for complete flash memory electrical characteristics. 19.1. programming the flash memory the simplest means of programming the flash memo ry is through the c2 interface using programming tools provided by silicon laboratories or a th ird party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section ?30. c2 interface? on page 244. the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands. before programming flash memory using movx, flash programming operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock regist er (flkey). the pswe bit remains set until cleared by software. for detailed guidelines on programming flash from firmware, please see section ?19.4. flash write and erase guidelines? on page 115. note: a minimum sysclk frequency is required for writing or erasing flash memory, as detailed in ?7. electrical characteristics? on page 39. to ensure the integrity of the flash contents, the on -chip vdd monitor must be enabled and enabled as a reset source in any system that includes code that writes and/or erases flash memory from software. fur- thermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor is disabled, or not enabled as a reset source, will ca use a flash error device reset. 19.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per- formed. the flkey register is det ailed in sfr definition 19.2. 19.1.2. flash erase procedure the flash memory is organized in 512-byte pages. th e erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: 1. save current interrupt state and disable interrupts. 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. 7. clear the pswe and psee bits. c8051f80x-83x 114 rev. 1.0 8. restore previous interrupt state. steps 4?6 must be repeated for each 512-byte page to be erased. note: flash security settings may prevent erasure of some flash pages, such as the reserved area and the page containing the lock bytes. for a summary of flash security settings and restrictions affecting flash erase operations, please see section ?19.3. security options? on page 114. 19.1.3. flash write procedure a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the recommended procedure for writing a si ngle byte in flash is as follows: 1. save current interrupt state and disable interrupts. 2. ensure that the flash byte has been erased (has a value of 0xff). 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. 8. clear the pswe bit. 9. restore previous interrupt state. steps 5?7 must be repeated for each byte to be written. note: flash security settings may prevent writes to some ar eas of flash, such as the reserved area. for a summary of flash security settings and restrictions affecting fl ash write operations, please see section ?19.3. security options? on page 114. 19.2. non-volati le data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read us ing the movc instruction. note: movx read instructions always target xram. 19.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and th e program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before soft- ware can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, and erases) by u nprotected code or the c2 in terface. the flash secu- rity mechanism allows the user to lock all flash page s, starting at page 0, by writing a non-0xff value to the lock byte. note that writing a non-0xff value to the lock byte will lock all pages of flash from reads, writes, and erases, including the page containing the lock byte. the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on rev. 1.0 115 c8051f80x-83x unlocked pages, and user firmware executing on locked pages. table 19.1 summarizes the flash security features of the c8051f80x-83x devices. 19.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of vdd, system clock frequency, or te mperature. this accidental execution of flash modi- fying code can result in alteration of flash memory contents causing a system failure that is only recover- able by re-flashing the code in the device. to help prevent the accidental modi fication of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on c8051f80x-83x devic es for the flash to be successfully modified. if either table 19.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted fedr permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted fedr permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted fedr permitted erase page containing lock byte (if no pages are locked) permitted fedr fedr erase page containing lock byte?unlock all pages (if any page is locked) only by c2de fedr fedr lock additional pages (change 1s to 0s in the lock byte) not permitted fedr fedr unlock individual pages (change 0s to 1s in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr c2de?c2 device erase (erases all flash pages including the page containing the lock byte) fedr?not permitted; causes flash error device reset (ferror bit in rs tsrc is 1 after reset) ? all prohibited operations that are performed via th e c2 interface are ignored (do not cause device reset). ? locking any flash page also locks the page containing the lock byte. ? once written to, the lock byte cannot be modifi ed except by performing a c2 device erase. ? if user code writes to the lock byte, the lock does not take effect until the next device reset. c8051f80x-83x 116 rev. 1.0 the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be generated when the firmware attempts to modify the flash. the following guidelines are recomme nded for any system that contains routines which write or erase flash from code. 19.4.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum vdd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external vdd brownout circuit to the rst pin of the device that holds the device in reset until vdd reaches the minimum device operating voltage and re-asserts rst if vdd drops below the minimum device operating voltage. 3. keep the on-chip vdd monitor enabled and enable the vdd monitor as a reset source as early in code as possible. this should be the fi rst set of instructions executed after the reset vector. for c-based systems, this will involve modifyin g the startup code a dded by the c compiler. see your compiler documentation for more details. make certain that th ere are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware," available from the silicon laboratories website. note: on c8051f80x-83x devices, both the vdd monitor and t he vdd monitor reset source must be enabled to write or erase flash without generatin g a flash error device reset. on c8051f80x-83x devices, both the vdd monitor and t he vdd monitor reset source are enabled by hardware after a power-on reset. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a reset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the in struction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use di rect assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc register explicitly set the porsf bi t to a 1. areas to check are initialization code which enab les other reset sources, such as the missing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 19.4.2. pswe maintenance 1. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a 1 to write flash bytes and one routine in code that sets both pswe and psee both to a 1 to erase flash pages. 2. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware," available from the silicon laboratories website. 3. disable interrupts prior to setting pswe to a 1 and leave them disabled until after pswe has been reset to 0. any inte rrupts posted during the flash write or er ase operation will be serviced in priority order after the flash operation has been completed a nd interrupts have been re-enabled by software. 4. make certain that the flash write and erase poin ter variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variab les in different memory areas. rev. 1.0 117 c8051f80x-83x 5. add address bounds checking to th e routines that write or erase flas h memory to ensure that a routine called with an illegal address does not result in modification of the flash. 19.4.3. system clock 1. if operating from an external crystal, be advised th at crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 2. if operating from the external oscillator, switch to the internal oscillator du ring flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code ca n be found in ?an201: writing to flash from firm- ware," available from the silicon laboratories website. c8051f80x-83x 118 rev. 1.0 sfr address =0x8f sfr definition 19.1. psctl: program store r/w control bit76543210 name psee pswe type rrrrrrr/wr/w reset 00000000 bit name function 7:2 unused read = 000000b, write = don?t care. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; the movx write instruction targets flash memory. rev. 1.0 119 c8051f80x-83x sfr address = 0xb7 sfr definition 19.2. flk ey: flash lock and key bit76543210 name flkey[7:0] type r/w reset 00000000 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases ar e enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis- ter. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disa bled, the flash will be perma- nently locked from writes or erasures until the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset. c8051f80x-83x 120 rev. 1.0 20. power management modes the c8051f80x-83x devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the hi gh-speed oscillator peripheral. idle mode halts the cpu while leavin g the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator an d cpu are halted, but the device can wake on events such as a port mismatch, comparator low output, or a timer 3 overflow. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 20.1 describes the power control register (pcon) used to contro l the c8051f80x-83x's stop and idle power manage- ment modes. suspend mode is cont rolled by the suspend bit in the oscicn register (sfr definition 22.3). although the c8051f80x-83x has idle, stop, and sus pend modes available, more control over the device power can be achieved by enabling/disabling individ ual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 20.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction imme diately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instruction following the write of the idle bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructions that set the idle bit should be followed by an instruction that has two or more opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi- nitely, waiting for an external stim ulus to wake up the system. refer to section ?29.4. watchdog timer mode? on page 236 for more information on the use and configuration of the wdt. rev. 1.0 121 c8051f80x-83x 20.2. stop mode setting the stop mode select bit (pcon.1) causes the co ntroller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circ uit) may be shut down individually prior to en tering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 s. 20.3. suspend mode suspend mode allows a system running from the internal oscillator to go to a very low power state similar to stop mode, but the processor can be awakened by certain events without requiring a reset of the device. setting the suspend bit (oscicn.5) causes the hardware to halt the cpu and the high-frequency inter- nal oscillator, and go into suspend m ode as soon as the inst ruction that sets the bit completes execution. all internal registers and memory main tain their original data. most digital peripherals are not active in sus- pend mode. the exception to this is the port match feature and timer 3, when it is run from an external oscillator source. the clock divider bits clkdiv[2:0] in register clksel must be set to "d ivide by 1" when entering suspend mode. suspend mode can be terminated by five types of events, a port match (described in section ?23.5. port match? on page 150), a timer 2 overflow (described in section ?28.2. timer 2? on page 219), a comparator low output (if enabled), a capacitive sense greater-than comparator event, or a device reset event. in order to run timer 3 in suspend mode, the timer must be configured to clock from the external clock source. when suspend mode is term inated, the device will continue execut ion on the instructi on following the one that set the suspend bit. if the wake event (port match or timer 2 overflow) was co nfigured to generate an interrupt, th e interrupt will be serviced upon waking the device. if suspend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: the device will still enter suspend mode if a wake source is "pending", and the device will not wake on such pending sources. it is important to ensure that the in tended wake source will trigger after the device enters suspend mode. for example, if a cs0 conversion comple tes and the interrupt fires before the device is in suspend mode, that interrupt cannot trigger the wake event. because port match events are level-sensitive, pre-existing port match events will trigger a wake, as long as the matc h condition is still present when the device enters suspend. c8051f80x-83x 122 rev. 1.0 sfr address = 0x87 sfr definition 20.1. pcon: power control bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip-51 in st op mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). 0idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.) rev. 1.0 123 c8051f80x-83x 21. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 21.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable c8051f80x-83x 124 rev. 1.0 21.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 21.2. plots the power-on and v dd monitor reset timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 10 ms. on exit from a power-on reset, the porsf flag (rst src.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem- ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled and selected as a reset source following a power-on reset. figure 21.2. power-on and v dd monitor reset timing power-on reset vdd monitor reset rst t v dd supply logic high logic low t pordelay v dd v rst v dd rev. 1.0 125 c8051f80x-83x 21.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 21.2). when v dd returns to a level above v rst , the cip-51 will be released fr om the reset state. even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if v dd dropped below the level required for data retention. if the porsf flag reads 1, the data may no longer be valid. the v dd monitor is enabled and selected as a reset source after power-on resets. its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. important note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: 1. enable the v dd monitor (vdmen bit in vdm0cn = 1). 2. if necessary, wait for the v dd monitor to stabilize. 3. select the v dd monitor as a reset source (porsf bit in rstsrc = 1). see figure 21.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see section ?7. electri cal characteristics? on page 39 for complete electrical characteristics of the v dd monitor. c8051f80x-83x 126 rev. 1.0 sfr address = 0xff 21.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induce d resets. see section ?7. e lectrical characteristics? on page 39 for complete rst pin specifications. the pinrsf flag (rstsr c.0) is set on exit from an exter- nal reset. 21.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit th at is triggered by the system clock. if the system clock remains high or low for more than the mcd timeout, t he one-shot will time ou t and generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; oth- erwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the mi ssing clock detector ; writing a 0 dis- ables it. the state of the rst pin is unaffected by this reset. sfr definition 21.1. vdm0cn: v dd monitor control bit7654321 0 name vdmen vddstat type r/wrrrrrr r reset varies varies varies varies varies varies varies varies bit name function 7vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys- tem resets until it is also selected as a reset source in register rstsrc (sfr def- inition 21.2). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. after a power-on reset, th e vdd monitor is enabled, and this bit will read 1. the state of this bit is sticky through any other reset source. 0: v dd monitor disabled. 1: v dd monitor enabled. 6vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5:0 unused read = varies; write = don?t care. rev. 1.0 127 c8051f80x-83x 21.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, th e c0rsef flag (rstsrc.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the rst pin is unaffected by this reset. 21.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as de scribed in section ?29.4. watchdog timer mode? on page 236; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 21.7. flash error reset if a flash read/write/e rase or program read target s an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx write operation targets an address above address 0x3dff. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x3dff. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above 0x3dff. ? a flash read, write or erase attempt is restrict ed due to a flash security setting (see section ?19.3. security options? on page 114). the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 21.8. software reset software may force a reset by wr iting a 1 to the swrsf bit (rstsr c.4). the swrsf bit will read 1 fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset. c8051f80x-83x 128 rev. 1.0 sfr address = 0xef sfr definition 21.2. r stsrc: reset source bit76543210 name ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r r r/w r/w r r/w r/w r reset 0 varies varies varies var ies varies varies varies bit name description write read 7 unused unused. don?t care. 0 6ferror flash error reset flag. n/a set to 1 if flash read/write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a 1 enables comparator0 as a reset source (active-low). set to 1 if comparator0 caused the last reset. 4swrsf software reset force and flag. writing a 1 forces a sys- tem reset. set to 1 if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a 1 enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a 1 enables the v dd monitor as a reset source. writing 1 to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to 1 anytime a power- on or v dd monitor reset occurs. when set to 1 all other rstsrc flags are inde- terminate. 0pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. note: do not use read-modify-write operations on this register rev. 1.0 129 c8051f80x-83x 22. oscillators and clock selection c8051f80x-83x devices incl ude a programmable internal high-frequency os cillator and an external oscilla- tor drive circuit. the internal hi gh-frequency oscillator can be enabled /disabled and calib rated using the oscicn and oscicl registers, as shown in figure 22.1. the system clock can be sourced by the exter- nal oscillator circuit or the internal oscillator (default). the in ternal oscillator offers a selectable post-scaling feature, which is initially set to divide the clock by 8. figure 22.1. oscillator options 22.1. system clock selection the system clock source for the mcu can be select ed using the clksel register. the clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. when switching between two clock divide values, the transition may take up to 128 cycles of the undivided clock source. the clkrdy flag can be polled to determine when the new clock divide value has been applied. the clock divider must be set to "divide by 1" when entering suspend mode. the system clock source may also be switched on-the-fly. the switchover takes effect after one cl ock period of the slower oscillator. clock divider osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ioscen ifrdy suspend stsync sse ifcn1 ifcn0 oscxcn xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 option 4 ? cmos mode xtal2 option 2 ? rc mode vdd xtal2 option 3 ? c mode xtal2 xtal1 xtal2 option 1 ? crystal mode 10m ? clksel clkdiv2 clkdiv1 clkdiv0 clkrdy clksl1 clksl0 clkrdy clock divider n c8051f80x-83x 130 rev. 1.0 sfr address = 0xa9 sfr definition 22.1. clksel: clock select bit7 6 543210 name clkrdy clkdiv[2:0] clksel[2:0] type r r/w r/w r/w r r/w r/w r/w reset 0 0 000000 bit name function 7clkrdy system clock divider clock ready flag. 0: the selected clock divide setting has not been applied to the system clock. 1: the selected clock divide setting has been applied to the system clock. 6:4 clkdiv system clock divider bits. selects the clock division to be applied to the selected source (internal or external). 000: selected clock is divided by 1. 001: selected clock is divided by 2. 010: selected clock is divided by 4. 011: selected clock is divided by 8. 100: selected clock is divided by 16. 101: selected clock is divided by 32. 110: selected clock is divided by 64. 111: selected clock is divided by 128. 3 unused read = 0b. must write 0b. 2:0 clksel[2:0] system clock select. selects the oscillator to be used as the undivided system clock source. 000: internal oscillator 001: external oscillator all other values reserved. rev. 1.0 131 c8051f80x-83x 22.2. programmable internal high-frequency (h-f) oscillator all c8051f80x-83x devices in clude a programma ble internal hi gh-frequency oscillator th at defaults as the system clock after a system reset. th e internal oscillator period can be adjusted via the oscicl register as defined by sfr definition 22.2. on c8051f80x-83x devices, osci cl is factory calibrated to ob tain a 24.5 mhz base frequency. the internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the ifcn bits in reg- ister oscicn. the divide value def aults to 8 following a reset. the precision oscillator supports a spread spectrum mode which modul ates the output frequency in order to reduce the emi generated by the system. when enabled (sse = 1) , the oscillator output frequency is modulated by a stepped triangle wave whose frequenc y is equal to the oscillato r frequency divided by 384 (63.8 khz using the factory calibration). the maximum dev iation from the center frequency is 0.75%. the output frequency updates occur every 32 cycles and th e step size is typically 0.25% of the center fre- quency. sfr address = 0xb3 sfr definition 22.2. oscicl: intern al h-f oscillator calibration bit76543210 name oscicl[6:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 6:0 oscicl[7:0] internal oscillator calibration bits. these bits determine the internal oscillato r period. when set to 00000000b, the h-f oscillator operates at its fa stest setting. when set to 111 11111b, the h-f osc illator operates at its slowest setting. the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 mhz. c8051f80x-83x 132 rev. 1.0 sfr address = 0xb2 sfr definition 22.3. oscicn: inte rnal h-f oscillator control bit76 5 43210 name ioscen ifrdy suspend stsync sse ifcn[1:0] type r/w r r/w r r/w r r/w reset 11 0 00000 bit name function 7ioscen internal h-f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is no t running at pr ogrammed frequency. 1: internal h-f oscillator is running at progr ammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter- nal oscillator resumes operation when one of the suspend mode awakening events occurs. 4 stsync suspend timer synchronization bit. this bit is used to indicate when it is sa fe to read and write the registers associated with the suspend wake-up timer. if a su spend wake-up source other than timer 2 has brought the oscillator out of suspend mode, it make ta ke up to three timer clocks before the timer can be read or written. 0: timer 2 registers can be read safely. 1: timer 2 register reads and writes should not be performed. 3sse spread spectrum enable. spread spectrum enable bit. 0: spread spectrum clock dithering disabled. 1: spread spectrum clock dithering enabled. 2 unused read = 0b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator fre quency divider control bits. 00: sysclk derived from internal h-f oscillator divided by 8. 01: sysclk derived from internal h-f oscillator divided by 4. 10: sysclk derived from internal h-f oscillator divided by 2. 11: sysclk derived from internal h-f oscillator divided by 1. rev. 1.0 133 c8051f80x-83x 22.3. external osci llator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the xtal1 and xt al2 pins as shown in op tion 1 of figure 22.1. a 10 m ?? resistor also must be wired across the xtal2 an d xtal1 pins for the crystal/resonator configura- tion. in rc, capacitor, or cmos clock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 22.1. the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 22.4). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal /resonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by t he oscillator circuit; see sect ion ?23.3. priority crossbar decoder? on page 143 for crossbar co nfiguration. additionally, when usin g the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?23.4. port i/o initialization? on page 147 for deta ils on port inpu t mode selection. c8051f80x-83x 134 rev. 1.0 sfr address = 0xb1 sfr definition 22.4. oscxcn: ex ternal oscillator control bit76543210 name xtlvld xoscmd[2:0] xfcn[2:0] type rr/wrr/w reset 00000000 bit name function 7xtlvld crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is u nused or not yet stable. 1: crystal oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for crystal or rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590khz 100khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4mhz 400khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 rev. 1.0 135 c8051f80x-83x 22.3.1. external crystal example if a crystal or ceramic resonator is us ed as an external osc illator source for the mcu, the circuit should be configured as shown in figure 22.1, option 1. the external oscillato r frequency cont rol value (xfcn) should be chosen from the crystal column of the ta ble in sfr definition 22.4 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b and a 32.768 khz watch crystal requires an xfcn setting of 001b. after an external 32.768 khz oscillator is st abilized, the xfcn setting can be switched to 000 to save power. it is recommended to enable the missing clock detector before switching the system clock to any external oscillator source. when the crystal oscillator is first enabled, the oscillator amplitude detec tion circuit requires a settling time to achieve proper bias. introduc ing a delay of 1 ms between enablin g the oscillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec- ommended procedure is as follows: 1. force xtal1 and xtal2 to a low state. this involv es enabling the crossbar and writing 0 to the port pins associated with xtal1 and xtal2. 2. configure xtal1 and xtal2 as analog inputs. 3. enable the external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld = 1. 6. if desired, enable the missing clock detector. 7. switch the system clock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to th e xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces whic h could introduce noise or interference. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the desired load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 22.1, option 1. the total value of the capacitors and the stray capac- itance of the xtal pins should equal 25 pf. with a st ray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 22.2. c8051f80x-83x 136 rev. 1.0 figure 22.2. external 32.768 khz quartz crystal oscillator connection diagram 22.3.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 22.1, option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to pr oduce the desired fr equency of oscillation, a ccording to eq uation 22.1, where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and r = the pull-up resistor value in k ? . equation 22.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 22.4, the required xfcn setting is 010b. xtal1 xtal2 10m ? 22pf* 22pf* 32.768 khz * capacitor values depend on crystal specifications f 1.23 10 3 ? rc ? ?? ? = rev. 1.0 137 c8051f80x-83x 22.3.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 22.1, option 3. the capacitor should be no gr eater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find the frequency of oscillation ac cording to equation 22.2, where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and v dd = the mcu power supply in volts. equation 22.2. c mode oscillator frequency for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 22.4 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf. fkf ?? rv dd ? ?? ? = c8051f80x-83x 138 rev. 1.0 23. port input/output digital and analog resources are available through 17 i/o pins (24-pin and 20-pin packages) or 13 i/o pins (16-pin packages). port pins p0.0?p 1.7 can be defined as general-purpose i/o (gpio) or assigned to one of the internal digital resources as shown in figure 23. 4. port pin p2.0 can be used as gpio and is shared with the c2 interface data signal (c2d). the desig ner has complete control over which functions are assigned, limited only by th e number of physical i/o pins. this re source assignment flexibility is achieved through the use of a priority crossbar decoder. note t hat the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 23.5). the registers xbr0 and xbr1, defined in sfr definition 23.1 and sfr definition 23.2, are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 23.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete electrical specifications for port i/o are given in section ?7. electrical characteristics? on page 39. figure 23.1. port i/o functional block diagram xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 2 cp0 outputs spi 4 p1.0 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 pnmdout, pnmdin registers p1.7* p2.0 to analog peripherals (adc0, cp0, vref, xtal) external interrupts ex0 and ex1 p1 i/o cells p2 i/o cells to cs0 *note: p1.4-p1.7 are not available on the 16-pin packages. rev. 1.0 139 c8051f80x-83x 23.1. port i/o m odes of operation port pins p0.0?p1.7 use the port i/o cell shown in figure 23.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin and pnmdout registers. port pin p2.0 can be con- figured by software for digital i/o using the p2mdout r egister. on reset, all port i/o cells default to a high impedance state with weak pull-ups enabled. until the cr ossbar is enabled (xbare = 1), both the high and low port i/o drive circuits are explic itly disabled on all crossbar pins. 23.1.1. port pins conf igured for analog i/o any pins to be used as comparator or adc input, capa citive sense input, external oscillator input/output, vref output, or agnd connection should be configured for analog i/o (pnmdin.n = 0, pn.n = 1). when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiver are disabled. to prevent the low port i/o drive circuit from pulling the pin low, a ?1? should be written to the corresponding port latch (pn.n = 1). port pins config ured for analog i/o will always read back a value of 0 regardless of the actual voltage on the pin. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital i/o may still be used by analog pe ripherals; however, this practice is not recom- mended and may result in measurement errors. 23.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, smbus, etc.), external digital event capture func- tions, or as gpio should be configured as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the vdd or gnd supply rails based on the out- put logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic va lue is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the vdd supply voltage to ensure the digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize power consumption and may be globally disabled by setting weakpud to 1. the user should ensure that digital i/o are always internally or externally pu lled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 23.2. port i/o cell block diagram gnd vio vio (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable) c8051f80x-83x 140 rev. 1.0 23.1.3. interfacing port i/o to 5 v logic all port i/o configured for digital, open-drain operatio n are capable of interfacing to digital logic operating at a supply voltage up to 2 v higher than vdd and less than 5.25 v. an external pull-up resistor to the higher supply voltage is typically required for most systems. important note: in a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150 a to flow into the port pin wh en the supply voltage is between (vdd + 0. 6v) and (vdd + 1.0v). once the port pin voltage increases beyond this range, the current flowing into the port pin is minimal. figure 23.3 shows the inpu t current characteristics of port pins driven above vdd. the port pin requires 150 a peak overdrive current when its voltage reaches approximately (vdd + 0.7 v). figure 23.3. port i/o overdrive current 23.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0?p1.7 can be assigned to various a nalog, digital, and external interrupt functions. the port pins assigned to analog functions should be config ured for analog i/o, and port pins assigned to digi- tal or external interrupt functions should be configured for digital i/o. 23.2.1. assigning port i/o pins to analog functions table 23.1 shows all available analog func tions that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and does no t allow it to be claimed by the crossbar. any selected pins should also have their corresponding bit in the port latch set to 1 (pn.n = 1). this prevents the low port i/o drive circuit from pulling th e pin low. table 23.1 shows the pot ential mapping of port i/o to each analog function. + - v test i vtest v dd i vtest (a) v test (v) 0 -10 -150 v dd v dd +0.7 i/o cell port i/o overdrive current vs. voltage port i/o overdrive test circuit rev. 1.0 141 c8051f80x-83x 23.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functions or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func- tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. table 23.2 shows all available digital functions and th e potential mapping of port i/o to each digital function. table 23.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignment adc input p0.0?p1.7 adc0mx, pnskip, pnmdin comparator0 input p0.0?p1.7 cpt0mx, pnskip, pnmdin cs0 input p0.0?p1.7 cs0mx, cs0ss, cs0se, pnmdin voltage reference (vref0) p0.0 ref0cn, p0skip, pnmdin ground reference (agnd) p0.1 ref0cn, p0skip external oscillator in crystal m ode (xtal1) p0.2 oscxcn, p0skip, p0mdin external oscillator in rc, c, or cr ystal mode (xtal2) p0.3 oscxcn, p0skip, p0mdin c8051f80x-83x 142 rev. 1.0 23.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (pnskip = 1) and pi ns in use by the crossbar (pnskip = 0). external digital event capture functions cannot be used on pi ns configured for analog i/o. table 23.3 shows all available external digital event capture functions. table 23.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment uart0, spi0, smbus, sysclk, pca0 (cex0-2 and eci), t0, or t1. any port pin available for assignment by the crossbar. this includes p0.0 - p1.7 2 pins which have their pnskip bit set to 0. 1 xbr0, xbr1 any pin used for gpio p0.0?p2.0 2 pnskip notes: 1. the crossbar will always assign uart0 pins to p0.4 and p0.5. 2. port pins p1.4 ?p1.7 are not available on the 16-pin packages. table 23.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for assignment external interrup t 0 p0.0?p0.7 it01cf external interrup t 1 p0.0?p0.7 it01cf port match p0.0?p1.7 * p0mask, p0mat p1mask, p1mat note: port pins p1.4 ?p1.7 are not available on the 16-pin packages. rev. 1.0 143 c8051f80x-83x 23.3. priority crossbar decoder the priority crossbar decoder assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the l east-significant unassigned port pin is assigned to that resource (exclud- ing uart0, which is always at pins 4 and 5). if a po rt pin is assigned, the crossbar skips that pin when assigning the next selected resource . additionally, the crossbar will skip po rt pins whose associated bits in the pnskip registers are set. the pnskip registers allow so ftware to skip port pins that are to be used for analog input, dedicate d functions, or gpio. because of the nature of the priority crossbar decoder, not all peripherals can be located on all port pins. figure 23.4 maps peripherals to the potential port pins on which the peripheral i/o can appear. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. th is applies to p0.0 if vr ef is used, p0.1 if agnd is used, p0.3 and/or p0.2 if the exte rnal oscillator circuit is enabled, p0 .6 if the adc is configured to use the external conversion start signal (cnvstr), and an y selected adc, comparator, or capacitive sense inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unas- signed pin. registers xbr0, xbr1, and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the cr ossbar assigns both pins associated with the smbus (sda and scl); when a uart is selected, the cross bar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for boot loading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. c8051f80x-83x 144 rev. 1.0 figure 23.4. priority crossbar decoder potential pin assignments tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 0 0 0 0 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss 2 0 1 2 3 6 1 p1 0 0 0 0 0 0 0 p1skip 0 p2 signal unavailable to crossbar pins p0.0-p1.7 1 are capable of being assigne d to crossbar peripherals. the crossbar peripherals are assigned in priority order from top to bottom, according to this diagram. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be ?skipped? by setting the corresponding bit in pnskip to ?1?. notes: 1. p1.4-p1.7 are not available on 16-pin packages. 2. nss is only pinned out when the spi is in 4-wire mode. cp0 cp0a 7 1 0 4 1 5 1 rev. 1.0 145 c8051f80x-83x figure 23.5. priority crossbar decoder example 1?no skipped pins tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 0 0 0 0 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss 2 0 1 2 3 6 1 p1 0 0 0 0 0 0 0 p1skip 0 p2 signal unavailable to crossbar in this example, the crossbar is configured to assign the uart tx0 and rx0 signals, the spi signals, and the pca signals. note that the spi signals are assigned as multiple signals, and there are no pins skipped using the p0skip or p1skip registers. these boxes represent the port pins which are used by the peripherals in this configuration. 1 st tx0 is assigned to p0.4 2 nd rx0 is assigned to p0.5 3 rd sck, miso, mosi, and nss are assigned to p0.0, p0.1, p0.2, and p0.3, respectively. 4 th cex0, cex1, and cex2 are assigned to p0.6, p0.7, and p1.0, respectively. all unassigned pins can be used as gpio or for other non-crossbar functions. notes: 1. p1.4-p1.7 are not available on 16-pin packages. 2. nss is only pinned out when the spi is in 4-wire mode. cp0 cp0a 7 1 0 4 1 5 1 c8051f80x-83x 146 rev. 1.0 figure 23.6. priority crossbar decoder example 2?skipping pins tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 1 0 1 1 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss 2 0 1 2 3 6 1 p1 0 0 0 0 0 0 0 p1skip 0 p2 signal unavailable to crossbar in this example, the crossbar is configured to assign the uart tx0 and rx0 signals, the spi signals, and the pca signals. note that the spi signals are assigned as multiple signals. additionally, pins p0.0, p0.2, and p0.3 are configured to be skipped using the p0skip register. these boxes represent the port pins which are used by the peripherals in this configuration. 1 st tx0 is assigned to p0.4 2 nd rx0 is assigned to p0.5 3 rd sck, miso, mosi, and nss are assigned to p0.1, p0.6, p0.7, and p1.0, respectively. 4 th cex0, cex1, and cex2 are assigned to p1.1, p1.2, and p1.3, respectively. all unassigned pins, including those skipped by xbr0 can be used as gpio or for other non-crossbar functions. notes: 1. p1.4-p1.7 are not available on 16-pin packages. 2. nss is only pinned out when the spi is in 4-wire mode. cp0 cp0a 7 1 0 4 1 5 1 p0.0 skipped p0.2 skipped p0.3 skipped rev. 1.0 147 c8051f80x-83x 23.4. port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all po rt pins, using the port in put mode register (pnmdin). if the pin is in analog mode, a ?1? must also be written to the corresponding port latch (pn) . 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals (xbr0, xbr1). 5. enable the cro ssbar (xbare = 1). all port pins must be configured as either analog or digital inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pi ns configured as digital inputs may still be used by analog peripher- als; however this practice is not recommended. additionally, all analog input pins should be config ured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all port pins in analog mode must have a ?1? set in the cor- responding port latch register. all pi ns default to digital inputs on reset. see sfr definition 23.8 and sfr definition 23.12 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr1 is 0, a weak pullup is enabled for all po rt i/o config- ured as open-drain. weakpu d does not affect the pu sh-pull port i/o. furthe rmore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, the c onfiguration wizard utility will determin e the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. c8051f80x-83x 148 rev. 1.0 sfr address = 0xe1 sfr definition 23.1. xbr0: port i/o crossbar register 0 bit76543210 name cp0ae cp0e syscke smb0e spi0e urt0e type r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 unused read = 00b. write = don?t care. 5cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 2smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 1spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. rev. 1.0 149 c8051f80x-83x sfr address = 0xe2 sfr definition 23.2. xbr1: port i/o crossbar register 1 bit7 6543210 name weakpud xbare t1e t0e ecie pca0me[1:0] type r/w r/w r/w r/w r/w r r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2 unused read = 0b; write = don?t care. 1:0 pca0me[1:0] pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. c8051f80x-83x 150 rev. 1.0 23.5. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft- ware controlled value stored in the pnmatch registers specifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the soft- ware controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 and p1 pins should be compared against the pnmatch regist ers. a port mismatch event is gene rated if (p0 & p0m ask) does not equal (p0match & p0mask) or if (p1 & p1mask) does not equal (p1match & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapte rs for more details on interrupt and wake-up sources. rev. 1.0 151 c8051f80x-83x sfr address = 0xfe sfr address = 0xfd sfr definition 23.3. p0mask: port 0 mask register bit76543210 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. sfr definition 23.4. p0mat: port 0 match register bit76543210 name p0mat[7:0] type r/w reset 11111111 bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mask which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high. c8051f80x-83x 152 rev. 1.0 sfr address = 0xee sfr address = 0xed 23.6. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding spec ial function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value writt en to the sfr is latched to main- tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pi n is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. sfr definition 23.5. p1mask: port 1 mask register bit76543210 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. note: p1.4?p1.7 are not available on 16-pin packages. sfr definition 23.6. p1mat: port 1 match register bit76543210 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mask which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. note: p1.4?p1.7 are not available on 16-pin packages. rev. 1.0 153 c8051f80x-83x each port has a corresponding pnskip register which allo ws its individual port pins to be assigned to dig- ital functions or skipped by the crossbar. all port pins used for analog functions or gpio should have their pnskip bit set to 1. the port input mode of the i/o pins is defined using the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is p2.0, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr address = 0x80; bit-addressable sfr definition 23.7. p0: port 0 bit76543210 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. c8051f80x-83x 154 rev. 1.0 sfr address = 0xf1 sfr address = 0xa4 sfr definition 23.8. p0mdi n: port 0 input mode bit76543210 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. in order for the p0.n pin to be in analog mode, there must be a ?1? in the port latch register corresponding to that pin. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 23.9. p0mdo ut: port 0 output mode bit76543210 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. rev. 1.0 155 c8051f80x-83x sfr address = 0xd4 sfr address = 0x90; bit-addressable sfr definition 23.10. p0skip: port 0 skip bit76543210 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. sfr definition 23.11. p1: port 1 bit76543210 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. note: p1.4?p1.7 are not available on 16-pin packages. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. c8051f80x-83x 156 rev. 1.0 sfr address = 0xf2 sfr address = 0xa5 sfr definition 23.12. p1mdin: port 1 input mode bit76543210 name p1mdin[7:0] type r/w reset 1*1*1*1*1111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. in order for the p1.n pin to be in analog mode, there must be a 1 in the port latch register corresponding to that pin. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. note: p1.4?p1.7 are not available on 16-pin packages, with the reset value of 0000b for p1mdin[7:4]. sfr definition 23.13. p1mdout: port 1 output mode bit76543210 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the corresponding bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. note: p1.4?p1.7 are not available on 16-pin packages. rev. 1.0 157 c8051f80x-83x sfr address = 0xd5 sfr address = 0xa0; bit-addressable sfr definition 23.14. p1skip: port 1 skip bit76543210 name p1skip[7:0] type r/w reset 0*0*0*0*0000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. note: p1.4?p1.7 are not available on 16-pin packages, with the reset value of 1111b for p1skip[7:4]. sfr definition 23.15. p2: port 2 bit76543210 name p2[0] type rrrrrrrr/w reset 00000001 bit name description write read 7:1 unused unused. don?t care 0000000b 0 p2[0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.0 port pin is logic low. 1: p2.0 port pin is logic high. c8051f80x-83x 158 rev. 1.0 sfr address = 0xa6 sfr definition 23.16. p2mdout: port 2 output mode bit7654321 0 name p2mdout[0] type rrrrrrr r/w reset 0000000 0 bit name function 7:1 unused read = 0000000b; write = don?t care 0p2mdout[0] output configuration bits for p2.0. 0: p2.0 output is open-drain. 1: p2.0 output is push-pull. rev. 1.0 159 c8051f80x-83x 24. cyclic redundancy check unit (crc0) c8051f80x-83x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit data written to the crc0in register. crc0 posts the 16-bit or 32-bit result to an internal register. the internal result register may be accessed indi- rectly using the crc0pnt bits and crc0dat regist er, as shown in figure 24.1. crc0 also has a bit reverse register for quick data manipulation. figure 24.1. crc0 block diagram crc0in 8 crc0dat crc0cn crc0sel crc0init crc0val crc0pnt1 crc0pnt0 crc engine 4 to 1 mux result 32 8 8 8 8 8 crc0auto crc0cnt automatic crc controller flash memory 8 crc0flip write crc0flip read c8051f80x-83x 160 rev. 1.0 24.1. 16-bit crc algorithm the c8051f80x-83x crc unit calculates the 16-bit crc msb-first, using a poly of 0x1021. the following describes the 16-bit crc algorithm performed by the hardware: 1. xor the most-significant byte of th e current crc result with the input byte. if this is the first iteration of the crc unit, the curren t crc result will be the set in itial value (0x 0000 or 0xffff). 2. if the msb of the crc result is set, left-shift the crc result, and then xor the crc result with the polynomial (0x1021). 3. if the msb of the crc result is not set, left-shift the crc result. 4. repeat at step 2 for the number of input bits (8). for example, the 16-bit c8051f80x-83x crc algo rithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input){ unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } return crc_acc; // return the final remainder (crc value) } table 24.1 lists example input values and the asso ciated outputs using the 16-bit c8051f80x-83x crc algorithm (an initial value of 0xffff is used): table 24.1. example 16-bit crc outputs input output 0x63 0xbd35 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166 rev. 1.0 161 c8051f80x-83x 24.2. 32-bit crc algorithm the c8051f80x-83x crc unit calcul ates the 32-bit crc using a poly of 0x04c11db7. the crc-32 algo- rithm is "reflected", meaning that all of the input bytes and the final 32-bit output ar e bit-reversed in the pro- cessing engine. the following is a descr iption of a simplified crc algorith m that produces results identical to the hardware: 1. xor the least-significant byte of the current crc result with the input byte. if this is the first iteration of the crc unit, the current crc result will be the set initial value (0x00000000 or 0xffffffff). 2. right-shift the crc result. 3. if the lsb of the crc result is set, xor the cr c result with the reflected polynomial (0xedb88320). 4. repeat at step 2 for the number of input bits (8). for example, the 32-bit c8051f80x-83x crc algo rithm can be described by the following code: unsigned long updatecrc (unsigned long crc_acc, unsigned char crc_input){ unsigned char i; // loop counter #define poly 0xedb88320 // bit-reversed version of the poly 0x04c11db7 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ crc_input; // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x00000001) == 0x00000001) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc >> 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc >> 1; } } return crc_acc; // return the final remainder (crc value) } table 24.2 lists example input values and the asso ciated outputs using the 32-bit c8051f80x-83x crc algorithm (an initial value of 0xffffffff is used): table 24.2. example 32-bit crc outputs input output 0x63 0xf9462090 0xaa, 0xbb, 0xcc 0x41b207b3 0x00, 0x00, 0xaa, 0x bb, 0xcc 0x78d129bc c8051f80x-83x 162 rev. 1.0 24.3. preparing fo r a crc calculation to prepare crc0 for a crc calculati on, software should select the desired polynomial and set the initial value of the result. two polynomials are available: 0x1021 (16-bit) and 0x04c11db7 (32-bit). the crc0 result may be initialized to one of two values : 0x00000000 or 0xffffffff. the following steps can be used to initialize crc0. 1. select a polynomial (set crc0sel to 0 for 32-bit or 1 for 16-bit). 2. select the initial result value (set crc0 val to 0 for 0x000000 00 or 1 for 0xffffffff). 3. set the result to its initia l value (write 1 to crc0init). 24.4. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more flash se ctors. the following steps can be used to automati- cally perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit in crc0auto. 4. write the number of flash sectors to pe rform in the crc calculation to crc0cnt. note: each flash sector is 512 bytes. 5. write any value to crc0cn (or or its contents with 0x00) to initiate the c rc calculation. the cpu will not execute code any additional code until the crc operation completes. 6. clear the autoen bit in crc0auto. 7. read the crc result using the procedure below. 24.5. accessing th e crc0 result the internal crc0 result is 32 -bits (crc0sel = 0b) or 16-bits (crc0sel = 1b). the crc0pnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the calculation re sult will remain in the internal cr0 result register until it is set, overwritten, or addi- tional data is written to crc0in. rev. 1.0 163 c8051f80x-83x sfr address = 0xce sfr definition 24.1. crc0cn: crc0 control bit76543210 name crc0sel crc0init crc0val crc0pnt[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused read = 000b; write = don?t care. 4 crc0sel crc0 polynomial select bit. this bit selects the crc0 polynomial and result length (32-bit or 16-bit). 0: crc0 uses the 32-bit polynomial 0x 04c11db7 for calcul ating the crc result. 1: crc0 uses the 16-bit polynomial 0x1021 for calculating the crc result. 3 crc0init crc0 result init ialization bit. writing a 1 to this bit initializes th e entire crc result based on crc0val. 2 crc0val crc0 set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of 1 to crc0init. 1: crc result is set to 0xfff fffff on write of 1 to crc0init. 1:0 crc0pnt[1:0] crc0 result pointer. specifies the byte of the crc result to be read/written on the next access to crc0dat. the value of these bits will auto -increment upon ea ch read or write. for crc0sel = 0: 00: crc0dat accesses bits 7?0 of the 32-bit crc result. 01: crc0dat accesses bits 15?8 of the 32-bit crc result. 10: crc0dat accesses bits 23?16 of the 32-bit crc result. 11: crc0dat accesses bits 31?24 of the 32-bit crc result. for crc0sel = 1: 00: crc0dat accesses bits 7?0 of the 16-bit crc result. 01: crc0dat accesses bits 15?8 of the 16-bit crc result. 10: crc0dat accesses bits 7?0 of the 16-bit crc result. 11: crc0dat accesses bits 15?8 of the 16-bit crc result. c8051f80x-83x 164 rev. 1.0 sfr address = 0xdd sfr address = 0xde sfr definition 24.2. crc 0in: crc data input bit76543210 name crc0in[7:0] type r/w reset 00000000 bit name function 7:0 crc0in[7:0] crc0 data input. each write to crc0in result s in the written data being computed into the existing crc result according to the crc algorithm described in section 24.1 sfr definition 24.3. crc0data: crc data output bit76543210 name crc0dat[7:0] type r/w reset 00000000 bit name function 7:0 crc0dat[7:0] crc0 data output. each read or write performed on crc0dat targets the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn). rev. 1.0 165 c8051f80x-83x sfr address = 0xd2 sfr address = 0xd3 sfr definition 24.4. crc0aut o: crc automatic control bit76543210 name autoen crccpt reserved crc0st[4:0] type r/w reset 01000000 bit name function 7autoen automatic crc calc ulation enable. when autoen is set to 1, any write to crc0cn will initiate an automatic crc starting at flash sector crc0st and continuing for crc0cnt sectors. 6 crccpt automatic crc calcul ation complete. set to 0 when a crc calculation is in progress. code execution is stopped during a crc calculation, ther efore reads from firmware will always return 1. 5 reserved must write 0. 4:0 crc0st[4:0] automatic crc calculation starting flash sector. these bits specify the flash sector to start the automatic crc calculation. the starting address of the first flash sector included in the automatic crc calculation is crc0st x 512. sfr definition 24.5. crc0cnt: c rc automatic flash sector count bit76543210 name crc0cnt[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 crc0cnt[5:0] automatic crc calculation flash sector count. these bits specify the number of flash sectors to include when performing an automatic crc calculation. the base address of the last flash sector included in the automatic crc calculation is equal to (crc0st + crc0cnt) x 512. c8051f80x-83x 166 rev. 1.0 24.6. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of eac h bit in a byte as shown in figure 24.1. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. sfr address = 0xcf sfr definition 24.6. crc 0flip: crc bit flip bit76543210 name crc0flip[7:0] type r/w reset 00000000 bit name function 7:0 crc0flip[7:0] crc0 bit flip. any byte written to crc0flip is read back in a bit-reversed order, i.e. the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the data read back will be 0x03. if 0x05 is written to crc0flip, the data read back will be 0xa0. rev. 1.0 167 c8051f80x-83x 25. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) pr ovides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 25.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien c8051f80x-83x 168 rev. 1.0 25.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 25.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 25.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance st ate when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 25.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 25.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on th e bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 dete rmines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 25.2, figure 25.3, and figure 25.4 for typica l connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?23. port input/output? on page 138 for general purpose port i/o and crossbar information. 25.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag rev. 1.0 169 c8051f80x-83x is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb- first into the master's shift register. when a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another ma ster is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 25.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 25.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active wh en nssmd1 (spi0cn.3) = 1. in th is mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 25.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. figure 25.2. multiple-master mode connection diagram figure 25.3. 3-wire single master and 3-wire single slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck c8051f80x-83x 170 rev. 1.0 figure 25.4. 4-wire single master mode and 4-wire slave mode connection diagram 25.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges . when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 25.4 shows a connection diagram between tw o slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 25.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss rev. 1.0 171 c8051f80x-83x 25.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be writte n.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 an d allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 25.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 25.5. for slave mode, the clock and data relationships are shown in figure 25.6 and figure 25.7. note that ckpha should be set to 0 on both the master and slave spi when communicat ing between two silicon labs c8051 devices. the spi0 clock rate register (spi 0ckr) as shown in sfr definition 25.3 controls the master mode serial clock frequency. this register is ignored wh en operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and t he serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. c8051f80x-83x 172 rev. 1.0 figure 25.5. master mode data/clock timing figure 25.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) rev. 1.0 173 c8051f80x-83x figure 25.7. slave mode data/clock timing (ckpha = 1) 25.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cf g configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi c8051f80x-83x 174 rev. 1.0 sfr address = 0xa1 sfr definition 25.1. spi0c fg: spi0 configuration bit7654321 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not sele cted). this bit does not indicate the instantaneous value at th e nss pin, but rather a de-glitched ver- sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been tran sferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 25.1 for timing parameters. rev. 1.0 175 c8051f80x-83x sfr address = 0xf8; bit-addressable sfr definition 25.2. spi0cn: spi0 control bit7654321 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0000011 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if spi interrupts are enabled, an inte rrupt will be gene rated. this bit is not automatically cleared by hardware, and must be cleared by software. 6wcol write collision flag. this bit is set to logic 1 if a write to spi0dat is attempted when txbmt is 0. when this occurs, the write to spi0dat will be i gnored, and th e transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5modf mode fault flag. this bit is set to logic 1 by hardware w hen a master mode co llision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be generat ed. this bit is not automatica lly cleared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware w hen the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi inte rrupts are enabled, an interr upt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 25.2 and section 25.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled. c8051f80x-83x 176 rev. 1.0 sfr address = 0xa2 sfr address = 0xa3 sfr definition 25.3. spi0ckr: spi0 clock rate bit7654321 0 name scr[7:0] type r/w reset 0000000 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver- sion of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 m hz and spi0ckr = 0x04, sfr definition 25.4. spi0dat: spi0 data bit7654321 0 name spi0dat[7:0] type r/w reset 0000000 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- ---------------------- ----------------- - = f sck 2000000 241 + ?? ? --------------- ----------- = f sck 200 khz = rev. 1.0 177 c8051f80x-83x figure 25.8. spi master timing (ckpha = 0) figure 25.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051f80x-83x 178 rev. 1.0 figure 25.10. spi slave timing (ckpha = 0) figure 25.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz rev. 1.0 179 c8051f80x-83x table 25.1. spi slave timing parameters parameter description min max units master mode timing (see figure 25.8 and figure 25.9) t mckh sck high time 1 x t sysclk ?ns t mckl sck low time 1 x t sysclk ?ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 25.10 and figure 25.11) t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns note: t sysclk is equal to one period of the device system clock (sysclk). c8051f80x-83x 180 rev. 1.0 26. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonomously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas- ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. the smbus peripheral can be fully driven by software (i.e., software ac cepts/rejects slave addresses, and generat es acks), or hardware slave address recognition and automatic ack gener ation can be enabled to minimize software overhead. a block dia- gram of the smbus peripheral and the associated sfrs is shown in figure 26.1. figure 26.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation rev. 1.0 181 c8051f80x-83x 26.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 26.2. smbus configuration figure 26.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus ma y operate at different voltage levels. the bi-direc- tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on th e bus is limited only by th e requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 26.2. typical smbus configuration 26.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 26.3). if the receiving device does not ack, the tran smitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5 v master device slave device 1 slave device 2 vdd = 3 v vdd = 5 v vdd = 3 v sda scl c8051f80x-83x 182 rev. 1.0 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and dire ction bit. if the trans- action is a write operation from th e master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction and free the bu s. figure 26.3 illustrates a typical smbus transaction. figure 26.3. smbus transaction 26.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is se nt by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 26.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?26.3.5. scl high (smbus free) timeout? on page 183). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmit s a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 26.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 26.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop rev. 1.0 183 c8051f80x-83x overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 26.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen- tation. 26.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is de termined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard- ware is acting as a data transmitter or receiver. wh en a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 26.5 for more details on transmis- sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. th e smb0cn register is described in section 26.4.2; table 26.5 provides a quick smb0cn decoding reference. 26.4.1. smbus conf iguration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbu s timing and timeout optio ns. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). c8051f80x-83x 184 rev. 1.0 the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 26.1. note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?28. timers? on page 209. equation 26.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 26.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 26.2. equation 26.2. typical smbus bit rate figure 26.4 shows the typical scl generation described by equation 26.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will ne ver exceed the limits defined by equation equation 26.1. figure 26.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 26.2 shows the min- table 26.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ ----------- - == bitrate f clocksourceoverflow 3 --------------- ----------------- ------------- - = scl timer source overflows scl high timeout t low t high rev. 1.0 185 c8051f80x-83x imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?2 6.3.4. scl low timeout? on page 182). th e smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count wh en scl is low. the timer 3 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 26.4). table 26.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. c8051f80x-83x 186 rev. 1.0 sfr address = 0xc1 sfr definition 26.1. smb0cf: smbus clock/configuration bit76543210 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 00000000 bit name function 7ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6inh smbus slave inhibit. when this bit is set to logic 1, the smbu s does not generate an interrupt when slave events occur. this effectively removes th e smbus slave from the bus. master mode interrupts are not affected. 5busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 26.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. 2smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 sm bus clock source periods. 1:0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 26.1. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow rev. 1.0 187 c8051f80x-83x 26.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 26.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta ar e both set (while in master mode ), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see table 26.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 26.4.2.1. software ack generation when the ehack bit in register smb0 adm is cleared to 0, the firmware on the device must detect incom- ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a tr ansmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, in dicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not writ e the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not ackn owledged, further slave events will be ignored until the next start is detected. 26.4.2.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack gen- eration is enabled. more detail about automatic slave address recognition can be found in section 26.4.3. as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored until the next start is detected, and no interrupt will be generated. table 26.3 lists all sources for hardware changes to the smb0cn bits. refer to table 26.5 for smbus sta- tus decoding using the smb0cn register. c8051f80x-83x 188 rev. 1.0 sfr address = 0xc0; bit-addressable sfr definition 26.2. smb0cn: smbus control bit76543210 name master txmode sta sto ackrq arblost ack si type rrr/wr/wrrr/wr/w reset 00000000 bit name description read write 7 master smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. n/a 6txmode smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. n/a 5sta smbus start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto smbus stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pend- ing (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3ackrq smbus acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost smbus arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si smbus interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1 : interrupt pending 0: clear interrupt, and initi- ate next state machine event. 1: force interrupt. rev. 1.0 189 c8051f80x-83x 26.4.3. hardware slave address recognition the smbus hardware has th e capability to automatica lly recognize incoming sl ave addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a ma ster or slave). more detail on automatic hardware ack generation can be found in section 26.4.2.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register (sfr definition 26.3) and the smbus slave address mask register (sfr definition 26.4). a single address or range of addresses (including the general call address 0x00) can be specified using these two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in bit positions of the slave address ma sk slvm[6:0] enab le a comparison between the received slave address and the hardware?s sl ave address slv[6:0] for those bits. a 0 in a bit of the slave address mask means that bit will be treated as a ?don?t care ? for comparison purposes. in this table 26.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low wh ile attempting to generate a stop or repeated start condition. ? sda is sensed low while transmitting a 1 (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. c8051f80x-83x 190 rev. 1.0 case, either a 1 or a 0 value are acceptable on the in coming slave address. additionally, if the gc bit in register smb0adr is set to 1, hardware will recogn ize the general call addres s (0x00). table 26.4 shows some example parameter settings and the slave addresses that will be reco gnized by hardware under those conditions. table 26.4. hardware address recognition examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c rev. 1.0 191 c8051f80x-83x sfr address = 0xd7 sfr address = 0xd6 sfr definition 26.3. smb0a dr: smbus slave address bit76543210 name slv[6:0] gc type r/w r/w reset 00000000 bit name function 7:1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0gc general call address enable. when hardware address reco gnition is enabled (ehack = 1), this bit will deter- mine whether the general call address (0 x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. sfr definition 26.4. smb0adm : smbus slave address mask bit76543210 name slvm[6:0] ehack type r/w r/w reset 11111110 bit name function 7:1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm[6:0] enables compari- sons with the corresponding bit in slv[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. c8051f80x-83x 192 rev. 1.0 26.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slav e receiver is made with the correct data or address in smb0dat. sfr address = 0xc2 sfr definition 26.5. smb0dat: smbus data bit76543210 name smb0dat[7:0] type r/w reset 00000000 bit name function 7:0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register. rev. 1.0 193 c8051f80x-83x 26.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. note that the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack genera- tion is enabled. as a transmitter, interrupts occur after the ack, regardless of whether hardware ack gen- eration is enabled or not. 26.5.1. write se quence (master) during a write sequence, an smbus ma ster writes data to a slave device . the master in th is transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bi t (r/w) will be logic 0 (write). the master then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written followin g a master transm itter interrupt. figure 26.5 shows a typical master write sequence. tw o transmit data bytes are shown, though any num- ber of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 26.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051f80x-83x 194 rev. 1.0 26.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data directi on bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the in terface will switch to mast er transmitter mode if smb0dat is written while an active master receiver. figure 26.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 26.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.0 195 c8051f80x-83x 26.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, th e hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave re ceiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0da t is written while an active slave rece iver. figure 26.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 26.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051f80x-83x 196 rev. 1.0 26.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans- mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit- ted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be generated if smb0dat is written followin g a received nack while in slave transmitter mode ). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0da t is not written following a slave transmitter interrupt. figure 26.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? inter- rupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 26.8. typical slave read sequence 26.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 26.5 descri bes the typical actions when hardware slave address recognition and ack generation is disabled. table 26. 6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ- ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi- cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.0 197 c8051f80x-83x table 26.5. smbus status decoding with hard ware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi cate last byte, and send stop. 010 ? send nack to indi cate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indi cate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100 c8051f80x-83x 198 rev. 1.0 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x lost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 11x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1001110 table 26.5. smbus status decoding with hardware ack generation disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.0 199 c8051f80x-83x table 26.6. smbus status decoding with hard ware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 c8051f80x-83x 200 rev. 1.0 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 01x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 10x1110 table 26.6. smbus status decoding with hardware ack generation enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.0 201 c8051f80x-83x 27. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?27.1. enhanced baud rate generation? on page 202). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the inte rrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 27.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) c8051f80x-83x 202 rev. 1.0 27.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 27.2), which is not user- accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 27.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit aut o-reload (see section ?28.1.3. mode 2: 8-bit coun- ter/timer with auto-reload? on page 212). the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate frequenc y. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, th e external oscillator cl ock/8, or an external input t1. for any given timer 1 clock source, the ua rt0 baud rate is determined by equation 27.1-a and equation 27.1-b. equation 27.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as descri bed in section ?28. timers? on page 209. a quick ref- erence for typical baud rates and system clock frequencies is given in table 27.1 through table 27.2. the internal oscillator may st ill generate the system cloc k when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------ ------------- - = a) b) rev. 1.0 203 c8051f80x-83x 27.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (sco n0.7). typical uart connection options are shown in figure 27.3. figure 27.3. uart interconnect diagram 27.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter- rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the st op-bit time). data recep- tion can begin any time after the re n0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over- run, the first received 8 bits are la tched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 27.4. 8-bit uart timing diagram or rs-232 c8051xxxx rs-232 level xltr tx rx c8051xxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space c8051f80x-83x 204 rev. 1.0 27.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these co nditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 fl ag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 27.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 rev. 1.0 205 c8051f80x-83x 27.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generat e an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the ua rt interrupt handler, software will compare the receiv ed address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is rece ived, the addressed slave resets its mce0 bit to ignore all transmis- sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 27.6. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ c8051f80x-83x 206 rev. 1.0 sfr address = 0x98; bit-addressable sfr definition 27.1. scon0: serial port 0 control bit76543210 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused read = 1b, write = don?t care. 5mce0 multiprocessor comm unication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is genera ted only when the ninth bit is logic 1. 4ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software. rev. 1.0 207 c8051f80x-83x sfr address = 0x99 sfr definition 27.2. sbuf0: seri al (uart0) port data buffer bit76543210 name sbuf0[7:0] type r/w reset 00000000 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch. c8051f80x-83x 208 rev. 1.0 table 27.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 28.1 . 2. x = don?t care. table 27.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 28.1 . 2. x = don?t care. rev. 1.0 209 c8051f80x-83x 28. timers each mcu includes three counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time in tervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 offers 16-bit and split 8-bit timer functionality with au to-reload. additionally, timer 2 offers the abil- ity to be clocked from the external oscillator while the device is in suspend mode, and ca n be used as a wake-up source. th is allows for implementation of a very low-power syste m, including rtc capability. timers 0 and 1 may be clocked by one of five source s, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 28.1 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc aled clock signal or the s ystem clock. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system clock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes timer 2 modes 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) c8051f80x-83x 210 rev. 1.0 sfr address = 0x8e sfr definition 28.1. ckcon: clock control bit76543210 name t2mh t2ml t1m t0m sca[1:0] type r r r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 unused read = 0b; write = don?t care 5t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defi ned by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock) rev. 1.0 211 c8051f80x-83x 28.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer cont rol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter (section ?18.2. interrupt register descriptions? on page 104); timer 1 interrupts can be enabled by set- ting the et1 bit in the ie register (section ?18. 2. interrupt register descriptions? on page 104). both counter/timers operate in one of four primary m odes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 28.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate a nd should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit in the tmod register selects the counte r/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pi n (t0) increment the timer register (refer to section ?23.3. priority crossbar decoder? on page 143 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0 m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocke d by the source selected by the clock scale bits in ckcon (see sfr definition 28.1). setting the tr0 bit (tcon.4) enables the timer when eit her gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01cf (see sfr definition 18.7). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?18.2. interrupt register descriptions? on page 104), facilitating pulse width measurements setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 18.7). tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care c8051f80x-83x 212 rev. 1.0 figure 28.1. t0 mode 0 block diagram 28.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 28.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bi t counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer overflow fl ag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 in the tmod regi ster is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf (see section ?18.3. int0 and int1 external interrupts? on page 111 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor t0m int0 t0 crossbar rev. 1.0 213 c8051f80x-83x figure 28.2. t0 mode 2 block diagram 28.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun- ter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is op erating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor t0 crossbar t0m int0 c8051f80x-83x 214 rev. 1.0 figure 28.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m rev. 1.0 215 c8051f80x-83x sfr address = 0x88; bit-addressable sfr definition 28.2. tcon: timer control bit76543210 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2it1 interrupt 1 type select. this bit selects whether the configured /int 1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 18.7). 0: /int1 is level triggered. 1: /int1 is edge triggered. 1ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 18.7). 0: int0 is level triggered. 1: int0 is edge triggered. c8051f80x-83x 216 rev. 1.0 sfr address = 0x89 sfr definition 28.3. tmod: timer mode bit76543210 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 18.7). 6c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high -to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 18.7). 2c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high -to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers rev. 1.0 217 c8051f80x-83x sfr address = 0x8a sfr address = 0x8b sfr definition 28.4. tl0: timer 0 low byte bit76543210 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 28.5. tl1: timer 1 low byte bit76543210 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. c8051f80x-83x 218 rev. 1.0 sfr address = 0x8c sfr address = 0x8d sfr definition 28.6. th0 : timer 0 high byte bit76543210 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 28.7. th1 : timer 1 high byte bit76543210 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. rev. 1.0 219 c8051f80x-83x 28.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 can also be used in capture mode to capture rising edges of the comparator 0 output. timer 2 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pc a) is clocked by an external oscilla- tor source. the external oscillator source divided by 8 is synchronized with the system clock when in all operating modes except suspend. wh en the internal oscillator is plac ed in suspend mode, the external clock/8 signal can directly drive the timer. this allows the use of an external clock to wake up the device from suspend mode. the timer will co ntinue to run in suspend mode and count up. when the timer over- flow occurs, the device will wake fr om suspend mode, and begin executing code again. the timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. if a wake-up source other than the time r wakes the device from suspend mode, it may take up to three timer clocks before the timer registers can be read or writ ten. during this time, the stsync bit in register oscicn will be set to 1, to indicate that it is not safe to read or write the timer registers. 28.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with au to-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16 -bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded in to the timer 2 register as shown in figure 28.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 28.4. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m c8051f80x-83x 220 rev. 1.0 28.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 28.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. timer 2 can also be used in capture mode to capture rising edges of the comparator 0 output. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 28.5. timer 2 8-bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m rev. 1.0 221 c8051f80x-83x 28.2.3. comparator 0 capture mode the capture mode in timer 2 allows comparator 0 rising edges to be captured with the timer clocking from the system clock or the system clock divided by 12 . timer 2 capture mode is enabled by setting tf2cen to 1 and t2split to 0. when capture mode is enabled, a capture event will be generated on every comparator 0 rising edge. when the capture event occurs, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers (tmr2rlh:tmr2rll) and the tf2h flag is set (triggering an interrupt if timer 2 inter- rupts are enabled). by recording the difference between two successive timer capture values, the comparator 0 period can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. this mode allows software to de termine the time between consecutiv e comparator 0 rising edges, which can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of a low-level analog signal. figure 28.6. timer 2 capture mode block diagram sysclk 0 1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt sysclk / 12 t2xclk external clock / 8 comparator 0 output 0 1 c8051f80x-83x 222 rev. 1.0 sfr address = 0xc8; bit-addressable sfr definition 28.8. tmr 2cn: timer 2 control bit76543210 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bi t causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 lo w byte interrupts. if ti mer 2 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 2 overflows. 4tf2cen timer 2 comparator capture enable. when set to 1, this bit enables timer 2 comparator capture mode. if tf2cen is set, on a rising edge of the comparator0 output the current 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2 rll. if timer 2 interrupts are also enabled, an interrupt will be generated on this event. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as tw o 8-bit auto-reload timers. 2tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care. 0t2xclk timer 2 external clock select. this bit selects the external clock source fo r timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: system clock divided by 12. 1: external clock divided by 8 (synchro nized with sysclk when not in suspend). rev. 1.0 223 c8051f80x-83x sfr address = 0xca sfr address = 0xcb sfr definition 28.9. tmr2rll: time r 2 reload register low byte bit76543210 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 28.10. tmr2rlh: ti mer 2 reload register high byte bit76543210 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. c8051f80x-83x 224 rev. 1.0 sfr address = 0xcc sfr address = 0xcd sfr definition 28.11. tmr2l: timer 2 low byte bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 28.12. tmr2h timer 2 high byte bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value. rev. 1.0 225 c8051f80x-83x 29. programmable counter array the programmable counter array (pca0) provides enh anced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between six sources: system clo ck, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre- quency output, 8 to 15-bit pwm, or 16-bit pwm (each mode is described in section ?29.3. capture/compare modules? on page 228). the external oscillator cl ock option is ideal for real-time clock (rtc) functionality, allowing the pca to be clocke d by a precision external oscillator while the inter- nal oscillator drives the system clock. the pca is co nfigured and controlled thr ough the system controller's special function registers. the pca block diagram is shown in figure 29.1 important note: the pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 29.4 for details. figure 29.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 c8051f80x-83x 226 rev. 1.0 29.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 29.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. figure 29.2. pca counter/timer block diagram table 29.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator sour ce divided by 8 (note) 1 1 x reserved note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 rev. 1.0 227 c8051f80x-83x 29.2. pca0 interrupt sources figure 29.3 shows a diagram of the pca interrupt tree . there are five independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an intermediat e overflow flag (covf), which can be set on an over- flow from the 8th through 15th bit of the pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, and ccf2), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pca0 interrup ts are globally enabled by setting the ea bit in the ie register and the epca0 bit in the eie1 register to logic 1. figure 29.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca counter/timer 8-bit through 15-bit overflow 0 1 set 8 through 15 bit operation pca0pwm a r s e l e c o v c l s e l 0 c l s e l 2 c l s e l 1 c o v f e a r 1 6 c8051f80x-83x 228 rev. 1.0 29.3. capture/compare modules each module can be configured to operate independ ently in one of six operat ion modes: edge-triggered capture, software timer, high-speed output, frequency output, 8-bit through 15-bit pulse width modulator, or 16-bit pulse width modulator. each module has specia l function registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 29.2 summarizes the bit settings in th e pca0cpmn and pca0pwm registers used to select the pca capture/compare mo dule?s operating mode. note that all modules set to use 8-bit through 15-bit pwm mode mu st use the same cycle l ength (8?15 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 29.2. pca0cpm and pca0pwm bit se ttings for pca capture/compare modules 1,2,3,4,5,6 operational mode pca0cpmn pca0pwm bit number7654321076543 2?0 capture triggered by positive edge on cexn xx10000a0 xbxxxxx capture triggered by negative edge on cexn xx01000a0 xbxxxxx capture triggered by any transition on cexn xx11000a0 xbxxxxx software timer xc00100a0 xbxxxxx high speed output xc00110a0 xbxxxxx frequency output xc00011a0 xbxxxxx 8-bit pulse width modulator 7 0 c 0 0 e 0 1 a 0 x b x x 000 9-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 001 10-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 010 11-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 011 12-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 100 13-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 101 14-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 110 15-bit pulse width modulator 7 0 c 0 0 e 0 1 a d x b x x 111 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b x 0 xxx 16-bit pulse width modulator with auto-reload 1 c 0 0 e 0 1 a d x b x 1 xxx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th through 15th bit overflow interrupt (depends on setting of clsel[2:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8-bit through 15-bit pwm mode use the same cycle length setting. rev. 1.0 229 c8051f80x-83x 29.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun- ter/timer and load it into the corresponding module 's 16-bit capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an inte rrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capn n bits are set to logic 1, then the state of the port pin associated wit h cexn can be read directly to de termine whether a rising-edge or fall- ing-edge caused the capture. figure 29.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x 000x x c8051f80x-83x 230 rev. 1.0 29.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a matc h occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interr upt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 29.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt rev. 1.0 231 c8051f80x-83x 29.3.3. high-speed output mode in high-speed output mode, a module?s associated ce xn pin is toggled each time a match occurs between the pca counter and the module's 16-bit capture/co mpare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0 cn is set to logic 1. an interrupt request is gen- erated if the ccfn interrup t for that module is enabled. the ccfn bit is not automatically cleared by hard- ware when the cpu vectors to the in terrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bits in the pca0cpmn regist er enables the high-speed output mode. if ecomn is cleared, the associated pin will retain its state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 29.6. pca high-speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt c8051f80x-83x 232 rev. 1.0 29.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 29.1. equation 29.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg- ister. the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when t he 16-bit pca0 counter an d the 16-bit capt ure/compare register for the chan- nel are equal. figure 29.7. pca frequency output mode 29.3.5. 8-bit through 15-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ- ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10, 11, 12 , 13, 14, or 15-bits). for backwards-compatibility with the 8-bit pwm mode available on other devices, the 8-bi t pwm mode operates slightly different than 9, 10, 11, 12, 13, 14, and 15-bit pwm modes. it is important to note that al l channels configured for 8-bit through 15-bit pwm mode w ill use the same cycle length. for example, it is no t possible to configure one channel for 8-bit pwm mode and another for 11-b it mode. however, other pca channels can be con- figured to pin capture, high-speed output, software timer, frequency output, or 16-bit pwm mode inde- pendently. f cexn f pca 2 pca 0 cphn ? ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset rev. 1.0 233 c8051f80x-83x 29.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figu re 29.8). also, when th e counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. this synchronous update feature allows software to asynchronously write a new pwm high time, whic h will then take effect on the following pwm period. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 000b enables 8-bit pulse width modulator mode. if the matn bit is set to 1, the ccfn flag for the module will be set ea ch time an 8-bit comparator match (r ising edge) occurs. the covf flag in pca0pwm can be used to de tect the overflow (fallin g edge), which will occur ev ery 256 pca clock cycles. the duty cycle for 8-bit pwm mode is given in equation 29.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.2. 8-bit pwm duty cycle using equation 29.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 29.8. pca 8-bit pwm mode diagram duty cycle 256 pca 0 cphn ? ?? 256 ------------------ ----------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf pca0pwm a r s e l e c o v c l s e l 0 c l s e l 2 c l s e l 1 c o v f e a r 1 6 0 x match c8051f80x-83x 234 rev. 1.0 29.3.5.2. 9-bit through 15-bit pulse width modulator mode the duty cycle of the pwm output signal in n-bit pwm mode (n=9 through 15) should be varied by writing to an ?auto-reload? register, which is dual-mapped into the pca0cphn and pca0cpln register loca- tions. the data written to define the duty cycle should be right-justified in the registers. the auto-reload registers are accessed (read or written) when the bi t arsel in pca0pwm is set to 1. the capture/com- pare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 coun ter match the value in the associated module?s cap- ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 29.9). upon an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload r egister is loaded into th e capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. this synchronous update feature allows software to asynch ronously write a new pwm high time, wh ich will then take effe ct on the following pwm period. the 9, 10, 11, 12, 13, 14, or 15-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in re gister pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the mo dule will be set each time a comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit), 2048 (11-bit), 4096 (12- bit), 8192 (13-bit) , 16384 (14-bit), or 32768 (15-bit) pca clock cycles. the duty cycle for n-bit pwm mode (n=9 through 15) is given in equation 29.2, where n is the numb er of bits in the pwm cycle. a 0% duty cycle ma y be generated by clearing the ecomn bit to 0. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.3. n-bit pwm duty cycle (n=9 through 15) figure 29.9. pca 9-bit through 15-bit pwm mode diagram duty cycle 2 n pca 0 cpn ? ?? 2 n ------------------ -------------- ----------- - = n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 2 c l s e l 1 c o v f e a r 1 6 x set ?n? bits: 001 = 9 bits 010 = 10 bits 011 = 11 bits 100 = 12 bits 101 = 13 bits 110 = 14 bits 111 = 15 bits x match rev. 1.0 235 c8051f80x-83x 29.3.6. 16-bit pulse width modulator mode a pca module may be operated in 16-bit pwm mode. 16 -bit pwm mode is independent of the other (8-bit through 15-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out- put on cexn is asserted high; when the 16-bit counte r overflows, cexn is asse rted low. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. the duty cycle of the pwm output signal can be vari ed by writing to an ?auto- reload? register, which is dual-mapped into the pca0cphn and pca0cpln regi ster locations. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. this synchronous update feature allows software to asynchro- nously write a new pwm high time, which will then take effect on the following pwm period. for backwards-compatibility with the 16-bit pwm mode available on ot her devices, the pwm duty cycle can also be changed without using the ?auto-reload? re gister. to output a varying duty cycle without using the ?auto-reload? register, new value writes shoul d be synchronized with pca ccfn match interrupts. match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare register writes. if the matn bit is se t to 1, the ccfn flag fo r the module will be set each time a 16-bit com- parator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycle for 16-bit pwm mode is given by equation 29.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.4. 16-bit pwm duty cycle using equation 29.4, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 29.10. pca 16-bit pwm mode duty cycle 65536 pca 0 cpn ? ?? 65536 ------------------ ------------------ ---------------- - = 16-bit comparator pca0h:l (auto-reload) pca0cph:ln cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 2 c l s e l 1 c o v f e a r 1 6 x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 (capture/compare) pca0cph:ln match xxx c8051f80x-83x 236 rev. 1.0 29.4. watchdog timer mode a programmable watchdog timer (wdt) function is av ailable through the pca module 2. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 2 operates as a watchdog timer (wdt). the mod- ule 2 high byte is compared to the pca counter high byte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option- ally re-configured and re-enabled if it is used in the system). 29.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 2 is forced into software timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca counter run control bit (cr) will re ad zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be up dated with a write of any value to pca0cph2. up on a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 29.11). figure 29.11. pca module 2 with watchdog timer enabled the 8-bit offset held in pca0cph2 is compared to th e upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a re set. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of th e pca0l when the update is performed. the total off- pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator rev. 1.0 237 c8051f80x-83x set is then given (in pca clocks) by equation 29.5, wher e pca0l is the value of the pca0l register at the time of the update. equation 29.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph2 and pca0h. software may force a wdt reset by writing a 1 to the ccf2 flag (pca0cn.2) while the wdt is enabled. 29.4.2. watchdog timer usage to configure the wdt, perform the following tasks: 1. disable the wdt by writing a 0 to the wdte bit. 2. select the desired pca clock source (with the cps2 ? cps0 bits). 3. load pca0cpl2 with the desi red wdt update offset value. 4. configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). 5. enable the wdt by setting the wdte bit to 1. 6. reset the wdt timer by writing to pca0cph2. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not se t, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 29.5, this results in a wdt timeout interval of 256 pca clock cycles, or 3072 sys tem clock cycles. table 29.3 lists some example time- out intervals for typical system clocks. 29.5. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. table 29.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8. offset 256 pca 0 cpl 2 ? ?? 256 pca 0 l ? ?? + = c8051f80x-83x 238 rev. 1.0 sfr address = 0xd8; bit-addressable sfr definition 29.1. pca0cn: pca0 control bit76543210 name cf cr ccf2 ccf1 ccf0 type r/w r/w r r r r/w r/w r/w reset 00000000 bit name function 7cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 unused read = 000b, write = don't care. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. rev. 1.0 239 c8051f80x-83x sfr address = 0xd9 sfr definition 29.2. pca0md: pca0 mode bit76543210 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 01000000 bit name function 7cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6wdte watchdog timer enable. if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog timer e nable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 11x: reserved 0ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. c8051f80x-83x 240 rev. 1.0 sfr address = 0xf7 sfr definition 29.3. pca0pwm : pca0 pwm configuration bit76543210 name arsel ecov covf ear16 clsel[1:0] type r/w r/w r/w r r/w r/w reset 00000000 bit name function 7arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9-bit through 15-bit pwm mode and 16-bit pwm mode. in all other modes, the auto -reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated when covf is set. 5covf cycle overflow flag. this bit indicates an overflow of the nth bit (n= 9 through 15) of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the clsel bits. the bit can be set by hardware or software, but must be cleared by software. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4 unused read = 0b; write = don?t care. 3 ear16 16-bit pwm auto-reload enable. this bit controls the auto-reload featur e in 16-bit pwm mode, which loads the pca0cpn capture/compare registers with th e values from the auto-reload registers at the same sfr addresses on an overflow of the pca counter (pca0). this setting affects all pca channels that are configured to use 16-bit pwm mode. 0: 16-bit pwm mode auto-reload is disabled . this default setting is backwards-com- patible with the 16-bit pwm mode available on other devices. 1: 16-bit pwm mode auto-reload is enabled. 2:0 clsel[2:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, from 8 to 15 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels configured to16-bit pwm mode. 000: 8 bits. 001: 9 bits. 010: 10 bits. 011: 11 bits. 100: 12 bits. 101: 13 bits. 110: 14 bits. 111: 15 bits. rev. 1.0 241 c8051f80x-83x sfr addresses: pca0cpm0 = 0xda , pca0cpm1 = 0xdb , pca0cpm2 = 0xdc sfr definition 29.4. pca0cpmn: pca0 capture/compare mode bit76543210 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 15-bit pwm selected. 1: 16-bit pwm selected. 6ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare regist er cause the ccfn bit in pca0md register to be set to logic 1. 2togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper- ates in frequency output mode. 1pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on th e cexn pin. 8 to 15-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm2 register cannot be modified, and module 2 acts as the watchdog timer. to change the contents of the pca0cpm2 register or the function of module 2, the watchdog timer must be disabled. c8051f80x-83x 242 rev. 1.0 sfr address = 0xf9 sfr address = 0xfa sfr definition 29.5. pca0l: pc a0 counter/timer low byte bit76543210 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register cannot be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 29.6. pca0h: p ca0 counter/timer high byte bit76543210 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will re ad the contents of a ?snapshot ? register, whose contents are updated only when the contents of pca0l are read (see section 29.1). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled. rev. 1.0 243 c8051f80x-83x sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec sfr definition 29.7. pca0cpln: pca0 capture module low byte bit76543210 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9-bit through 15-bit pwm mode and 16-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 29.8. pca0cphn: pca0 capture module high byte bit76543210 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca channel?s auto-reload value for 9-bit through 15-bit pwm mode and 16-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1. c8051f80x-83x 244 rev. 1.0 30. c2 interface c8051f80x-83x devices incl ude an on-chip silicon labs 2-wire (c2) debug interface to allow flash pro- gramming and in-system debugging with the production pa rt installed in the end a pplication. the c2 inter- face operates using only two pins: a bi-directional da ta signal (c2d), and a clock input (c2ck). see the c2 interface specification for details on the c2 protocol. 30.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec- ification. c2 register definition 30.1. c2add: c2 address bit76543210 name c2add[7:0] type r/w reset 00000000 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 in terface to select the target data register for c2 data read and data write commands. address name description 0x00 deviceid selects the device id register (read only) 0x01 revid selects the revision id register (read only) 0x02 fpctl selects the c2 flash programming control register 0xbf fpdat selects the c2 flash data register 0xd2 crc0auto* selects the crc0auto register 0xd3 crc0cnt* selects the crc0cnt register 0xce crc0cn* selects the crc0cn register 0xde crc0data* selects the crc0data register 0xcf crc0flip* selects the crc0flip register 0xdd crc0in* selects the crc0in register *note: crc registers and functions are described in section ?24. cyclic redundan cy check unit (crc0)? on page 159 . rev. 1.0 245 c8051f80x-83x c2 address: 0x00 c2 address: 0x01 c2 register definition 30. 2. deviceid: c2 device id bit76543210 name deviceid[7:0] type r/w reset 11100001 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x23 (c8051f80x-83x). c2 register definition 30. 3. revid: c2 revision id bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a. c8051f80x-83x 246 rev. 1.0 c2 address: 0x02 c2 address: 0xbf c2 register definition 30.4. fpct l: c2 flash programming control bit76543210 name fpctl[7:0] type r/w reset 00000000 bit name function 7:0 fpctl[7:0] c2 flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. once c2 flash programming is enabled, a system reset must be issued to resume normal operation. c2 register definition 30.5. fp dat: c2 flash programming data bit76543210 name fpdat[7:0] type r/w reset 00000000 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase rev. 1.0 247 c8051f80x-83x 30.2. c2ck pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface ca n safely ?borrow? the c2ck (rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 30.1. figure 30.1. typical c2 pin sharing the configuration in figure 30.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx c8051f80x-83x 248 rev. 1.0 d ocument c hange l ist revision 0.2 to revision 1.0 ? updated electrical specification tables to reflect production characterization data. ? added minimum sysclk specificati on for writing or erasing flash. ? added caution for going into suspend with wake source active (section 20.3) ? corrected vdm0cn reset values to "varies". ? removed mention of idac in pinout table. rev. 1.0 249 c8051f80x-83x n otes : c8051f80x-83x 250 rev. 1.0 c ontact i nformation silicon laboratories inc. silicon laboratories inc. 400 west cesar chavez austin, tx 78701 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs ar e trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes wi thout further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assu me any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability , including without limitation consequential or in cidental damages. silicon laboratories product s are not designed, intended, or authorized for us e in applications intended to support or sust ain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: silicon laboratories: ? keymatek? toolstick800dc |
Price & Availability of C8051F831-GS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |